Hi, all. This is Tomoya greeting from Japan.
I would like to hear about Altera Stratix-II ES(engineering sample)/MP(mass production) differences.
Here is background of our isse (we're facing); We'd made three DDR evaluation boards using Altera Stratix-II EP2S180/130. It has DDR interface, DDR memories, and many IOs (GPIO: General purpose IO). At first, we used EP2S180/130ES (engineering sample, working sample) because of delivery. It worked well. DDR worked well and GPIO ran at 200 MHz (or more) data communication speed between one board to another board (board to board).
After that, we'are now making same evaluation set. We use same PCB bare board, same devices/parts ... only differences are that we used EP2S180/130MS (mass production. Of course, same speed grade!).
However, the new one does not work well. It works when we drop its speed (from 200 to 150 MHz). We're now guessing it has clock problem. Especially, FPGA internal PLL.
Does anyone has had/faced same issue? Does anyone knows any differences between ES and MP of EP2S180/130?
If you have any issue/information about these, let me know. It helps our work and of cource I would like to post it for your progresses.
Best regards,