As I know ,in spartan 2e fpga ,There is no bufgmux,and I want to use clock mux in the design,can some give me some advice.If I can use a general mux to mux the two input clock and make the output clock use the global routing resource?
This is the second time I can refer someone to Peter's nice article, "Six Easy Pieces": Search the Xilinx website, when you find it, look at the sixth piece.
Here's a code snippet: Clk_A_Proc: process( Clk_A ) begin if FALLING_EDGE( Clk_A ) then Use_Clk_A
Thansks,I want to know what speed the Clock you list above can reach?
50Mhz?I care the sklew when routing!You should be able to run 200 MHz, but make sure that the clock multiplexer is confined to a small area. And then use Global Clock lines... Peter Alfke
50MHz is easy...it has a half period of 10ns, and I think it's very hard to get a net delay differential that large in today's parts. I said be careful about the delay on "Use_Clk_x" before, I meant the difference in delay between Use_Clk_x and Clk_x at the FF and at the LUT that does the multiplexing. Take a good close look at the circuit, understand it, I can't give you everything.
That said, you may want to implement it by instantiating the FF's and the LUT that does the multiplexing, and then applying LOCs or RLOCs to them, instead of inferring the devices as in the code snippet I gave. That way, you can be sure the FFs are close to the LUT. Finally, to be absolutely sure, you can verify with a post route back-annotated timing simulation. But this is probably overkill for 50MHz. I'll let you tell me what speed clock _you_ can reach.
50MHz is easy...it has a half period of 10ns, and I think it's very hard to get a net delay differential that large in today's parts. I said be careful about the delay on "Use_Clk_x" before, I meant the difference in delay between Use_Clk_x and Clk_x at the FF and at the LUT that does the multiplexing. Take a good close look at the circuit, understand it, I can't give you everything.
That said, you may want to implement it by instantiating the FF's and the LUT that does the multiplexing, and then applying LOCs or RLOCs to them, instead of inferring the devices as in the code snippet I gave. That way, you can be sure the FFs are close to the LUT. Finally, to be absolutely sure, you can verify with a post route back-annotated timing simulation. But this is probably overkill for 50MHz. I'll let you tell me what speed clock _you_ can reach.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.