clock hold time problems reported in quartus II

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Quartus II is reporting a clock hold time violation in a circuit which
may be described by the following diagram:

    --------           --------
    d   FF q--[logic]--d   FF q
   -clk    |          -clk    |
  | --------         | --------
  |                  |
--o------------------

I understand that the problem is that the input d of the second FF
changes too early after the common clock edge. However, somewhere else
in the same circuit I have the following

    --------           --------
    d   FF q-----------d   FF q
   -clk    |          -clk    |
  | --------         | --------
  |                  |
--o------------------

and quartus II does _not_ report any hold time violation here, and
obviously enough, the situation is even worse.

Something similar appears if I build a divide by 2:
a) directly (inverted q to d) or
b)using a 1 bit wide lpm_counter.
In the first case, I get a hold time violation and everything is ok in
the second case.

Perhaps someone can provide some insight into the following questions:

1. Is something inherently wrong with the first schematic? I even
thought it was always good idea to resynchronize signals in a similar
way.

2. In case this approach is ok, why does quartus II report clock hold
time problems?

3. If applicable, what should I tell the quartus II timing analyzer to
get rid of this error?

Thanks,
Pere


Re: clock hold time problems reported in quartus II
The circuits look fine, my guess is that you made a clock that isn't
using the global routing and based on the luck of the draw one circuit
meets hold time and the other doesn't.  If you are making a clock using
the general logic make sure you put onto a dedicated clock net before
use.  That way it will meet hold time by architecture instead of luck.

Jay

oopere wrote:
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Re: clock hold time problems reported in quartus II
snipped-for-privacy@yahoo.com ha escrito:

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Thanks for your reply.
Both parts of the circuit use the same clock signal. For this clock
signal I have also tried to add an assignment of the type: "global
signal" "global clock" "yes" with no success. (Before of this I only
had: "auto global clock" "on" "yes" which I thought was sufficient).

Is there any other way to "put onto a dedicated clock net" as you
suggested?

Pere


Re: clock hold time problems reported in quartus II
Also, look at the multi-cycle hold in the help section of Quartus.


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Re: clock hold time problems reported in quartus II
Rob ha escrito:

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Rob,
Thnaks for the reply. However, as I understand it, multi-cycle hold
assignments only would make sense if the processing took more than on
clock cycle (correct me if I'm wrong).
In this case, the hold time violation is because the processing is too
_fast_ causing the input to FF2 change to fast after it's clock edge.

Pere


Re: clock hold time problems reported in quartus II
Click on Assignments->Settings->Fitter Settings and set the "Optimize Hold
Timing" drop down to All Paths.The default value for the "Optimize Hold
Timing" drop dow is I/O Paths and Minimum tpd paths.

Hope this helps,
Subroto Datta
Altera Corp.

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