CLOCK GENERATOR

Hi every body I want to creat a VHDL code in order to generate 576 clocks. The range of clocks frequency is [3 kHz to 75 kHz] and each of them has 125 Hz frequency difference. Can any body help me?I would appreciate it.

Reply to
mahdi
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Unless you use an analog PLL you will have some output jitter. Let's assume you can tolerate 4 ns of jitter ( one part in 3000 at your top frequency.) Then you build a 20 bit binary accumulator, continuously add the desired multiple of 125 Hz (i.e. the value between 24 and 600, but expressed in binary) to the LSB end of the accumulator. The MSB of the accumulator is your desired output frequency, provided you clock the accumulator with a clock frequency of 250 Hz times

2exp20, which is 262.144 MHz, a reasonable clock frequency which maximizes the jitter to less than 4 ns. If you modify the accumulator to be decimal, you can use a more convenient even clock frequency. Food for thought! This technique is called Direct Digital Synthesis, or DDS. Peter Alfke
Reply to
Peter Alfke

Another alternative, is to search for Binary rate multiplier.

These devices are ideal for Hz-linear frequency generation, you target 125Hz multiples, and as Peter says, choose N= 24..600 of that, so you need a 10 bit rate multiplier (can be binary, or decimal) and a post-scaler. The post scaler reduces the jitter, so taking the 4ns example, that's ~250MHz of input clock. Peter's 262.144Mhz with a binary N/1024 RM, and /2048 (2^11) postscaler. or 256.00Mhz, if you use a decimal N/1000 RM, and a /2048 postscaler. Modern FPGAs are good at adding, but I think the simpler structure of the Rate Multiplier will out-speed the adder. Not sure which would give lowest power ?

-jg

Reply to
Jim Granville

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