Clock generator

Dear All,

Is it possible to generate 1843200 Hz clock using a 10 MHz clock in vhdl. If yes, would it be possible to give me the algorithm and I will try to implement it. I did a clock divider, but it does work only when the quotient is a power of 2.

Looking forward to hear from u,

Best regards, John.

Reply to
John
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contains a perl script that generates fractional-N dividers in both VHDL and Verilog.

It used 28 ff for your exact frequency ratio.

Relaxing the frequency tolerance to 0.1% (this is a baud rate generater, right?) reduced the size to 12 ff.

Regards, Allan.

Reply to
Allan Herriman

Thank you Allan, I generated the .vhd code, I will test, hope it will work.

Yes, it is a baud rate generator. it is 16*115200 Hz requirement of the uart trans/receiver.

Best regards, Ahmad.

Reply to
John

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