Hello all...
I am using a Xilinx Vitex II FPGA to unwrap a G.709 signal (OTU1) and output the underlying STM-16 (or other CBR2G5 signal).
The synchronous payload case is easy- I can use a DCM to generate a clock from the incoming data's recovered clock, and use that to clock out the data from an asynchronous FIFO filled by the unwrapping logic.
However, the asynchronous payload case seems undoable to me within the FPGA. Since the asynchronous payload could vary by +/- 65 ppm from the equivalent synchronous payload, I need to use the asynchronous data to generate a new clock, or use FIFO level measurement to fine tune the frequency of the outgoing clock. If I try to use the clock derived from the input clock, the FIFO could at worst start to over/underflow after about 1/10th second.
Lastly, if it really can't be done in an FPGA, what type of part could be used in tandem that would allow clock generation from a data stream that is accompanied by a valid signal?
Thanks!