Hi,
we all know how to count to 10 right?
I did think I can at least until I did see how a binary counter works in Spartan3e - I am still confused: the code in FPGA is at the end of the message, it really is a very normal counter and should count
0,1,2,3,4,5,6,7... ?
well it doesnt, it counts
0,5,2,3,4,1,6,7... !
I have verified this behaviour multiply times and its still counting this weird sequence where 1 and 5 are changed.
strange thing is that when I load the FPGA after loading the counter design with another known good bitstream then the second design works incorrectly about half of the outputs are not toggling. This only happens when configuring with non-impact tools. When the 2 designs are loaded with impact then the second works properly. The weird counter works the weird way no matter what tool is used to load the FPGA.
So as a real new year surprise I have now really seen an FPGA that gets configured with partial/damaged bitstream and still starts and reports done=1
Any suggestions what is wrong? Is my counter RTL code wrong?
I have tested the wrong count both from my program and with impact in JTAG debug mode, it really really counts wrong.
It can be that the FPGA is internally damaged as it was almost the only IC that survived after on-board switching supply got holes into the plastic and Strataflash failed to respond to QRY (partially damaged still responds to ID read).
hum when I have known fabric failing FPGA then its really nice to work on FPGA test patterns to see if they catch the failure
Antti
--------------- cut here --------------------- LED(6 downto 0)