What would be the proper way to clock a register at a fixed multiple of the system clock? I am trying to create a signal that is active around the rising edge of the system clock as a clock enable. I am using a counter to generate a signal at the time interval of interest. I am then performing an edge detection to get a signal that is active for a single system clock cycle. To get the enable centered around the rising edge of the system clock, I am clocking the edge detector with an inverted system clock. I have read not to use anything other than the system clock as the clock signal to a flip flop, so I am uncomfortable using the inverted clock. Is the inverted clock ok? Does anyone have any recommendations on a better way to do this.
library ieee; use ieee.std_logic_1164.all;
entity edge_detector is port ( clock : in std_logic; d : in std_logic; rising_edge_out : out std_logic ); end;
architecture behavioral of edge_detector is signal sreg : std_logic_vector(1 downto 0); begin edge_detector_proc : process(clock) begin if rising_edge(clock) then if sreg(1 downto 0) = "01" then rising_edge_out clock_divided_i, rising_edge_out => clock_enable_clock_divided );
inverted_clock