clock enable for fixed interval

What would be the proper way to clock a register at a fixed multiple of the system clock? I am trying to create a signal that is active around the rising edge of the system clock as a clock enable. I am using a counter to generate a signal at the time interval of interest. I am then performing an edge detection to get a signal that is active for a single system clock cycle. To get the enable centered around the rising edge of the system clock, I am clocking the edge detector with an inverted system clock. I have read not to use anything other than the system clock as the clock signal to a flip flop, so I am uncomfortable using the inverted clock. Is the inverted clock ok? Does anyone have any recommendations on a better way to do this.

library ieee; use ieee.std_logic_1164.all;

entity edge_detector is port ( clock : in std_logic; d : in std_logic; rising_edge_out : out std_logic ); end;

architecture behavioral of edge_detector is signal sreg : std_logic_vector(1 downto 0); begin edge_detector_proc : process(clock) begin if rising_edge(clock) then if sreg(1 downto 0) = "01" then rising_edge_out clock_divided_i, rising_edge_out => clock_enable_clock_divided );

inverted_clock

Reply to
Jim
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Hi Jim, using clock enables for multirate systems is a proper way, but you are trying to do it unneccessary complicated. It is much simpler.

You have a master clock, and a counter that provides the neccessary frequency division. So far so good. Now you only need to create an impulse for a single clock period. This can be done like this:

clock_divider_counter_proc: process (reset, clock) begin if reset =3D '1' then count '0'); clock_divided_i

Reply to
backhus

I'll let others comment on the overall strategy. Just want to point out that you can clock on negative edges ... "if falling_edge(clk) then " So an inverted clock is unnecessary.

- Brian

Reply to
Brian Drummond

Once you have the counter, then the clock enable is simply...

Clock_Enable around the rising edge of the system clock, I am clocking the edge

Simple synchronous logic like what you're describing here will never need anything more than the rising edge of one clock. Falling edges are rarely needed.

Kevin Jennings

Reply to
KJ

Your approach is flawed. It will not work well because it is not in line with the generally accepted way of FPGA programming. It uses asynchronous logic, which is frowned upon because the tools don't support it well. Insisting on using asynchronous logic will do you no favor.

It's perfectly valid that you want a clock-enable. However, it's unusual that you want the clock-enable to be centered "around the clock edge". It probably stems from working with discrete chips, where THAT was most reliable way to enable clocks.

In logic (discrete or FPGA), it's also possible to "enable" clocks by adding the enable as extra logic input, plus feedback of the previous output. Then you can "always clock" the register, yet make it only accept (honor) the change when "enable" is active. From the logic point of view, this is equivalent to a real clock-enable. But from other points of view, like for example power consumption, it may not be.

Yet it is good enough, and it helps achieving another goal: make a whole design from nothing but synchronous logic! This has been a major milestone in FPGA architecture. It's so much easier to do timing analysis on purely synchronous designs. In fact, the current tools do almost exclusively synchronous analysis ("static timing"). It was easier to make designs synchronous, than to make the tools handle asynchronous designs..

Using synchronous logic is very important for you. If you have any timing problems with your design, then you've either not read the timing report, or you've used non-synchronous tricks and are about to regret them.

Your desire to enable clocks is very wide spread, and so the FPGA makers have implemented support for their synchronous equivalent, right in the hardware. The necessary extra logic input and the feedback of the previous state is "free" in all modern (and not so modern) FPGAs. There is dedicated circuitry just for this purpose.

The following code shows how to register something on every other cycle. The tools will recognize it and use none of "your" resouces for it.

process (clk) begin if rising_edge(clk) then clkenable

Reply to
Marc Jet

Your approach is flawed. It will not work well because it is not in line with the generally accepted way of FPGA programming. It uses asynchronous logic, which is frowned upon because the tools don't support it well. Insisting on using asynchronous logic will do you no favor.

It's perfectly valid that you want a clock-enable. However, it's unusual that you want the clock-enable to be centered "around the clock edge". It probably stems from working with discrete chips, where THAT was most reliable way to enable clocks.

In logic (discrete or FPGA), it's also possible to "enable" clocks by adding the enable as extra logic input, plus feedback of the previous output. Then you can "always clock" the register, yet make it only accept (honor) the change when "enable" is active. From the logic point of view, this is equivalent to a real clock-enable. But from other points of view, like for example power consumption, it may not be.

Yet it is good enough, and it helps achieving another goal: make a whole design from nothing but synchronous logic! This has been a major milestone in FPGA architecture. It's so much easier to do timing analysis on purely synchronous designs. In fact, the current tools do almost exclusively synchronous analysis ("static timing"). It was easier to make designs synchronous, than to make the tools handle asynchronous designs..

Using synchronous logic is very important for you. If you have any timing problems with your design, then you've either not read the timing report, or you've used non-synchronous tricks and are about to regret them.

Your desire to enable clocks is very wide spread, and so the FPGA makers have implemented support for their synchronous equivalent, right in the hardware. The necessary extra logic input and the feedback of the previous state is "free" in all modern (and not so modern) FPGAs. There is dedicated circuitry just for this purpose.

The following code shows how to register something on every other cycle. The tools will recognize it and use none of "your" resouces for it.

process (clk) begin if rising_edge(clk) then clkenable

Reply to
Marc Jet

Eilert,

Thanks for the quick response. After I posted, I read that FPGAs typically have 0 hold times so your approach seems great. Thanks for the help.

Reply to
Jim

Hi Jim, well, it should be good, because it's been recommended in some XILINX papers and used in their System Generator tool as the default method for multirate systems. :-)

Have a nice synthesis Eilert

Reply to
backhus

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