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clock detection

Hi I need advice to build a very small firmware which will detect if clock signal is active or not Indeed, My FPGA (V2Pro) is connected to other devices/boards an receives a clock signal. However, this clock signal is not active a the begining and I would like to inform other devices/boards if cloc signal is ready or not

My question is : How can I do to know if a signal clock is active

I thought to implement a counter driven by this clock. But this wil

not ensure me that signal is a clock at X MHz

May I use a DCM, and look at the LOCKED signal

All ideas are welcomed

Thank you

Reply to
seb_tech_fr
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Hi seb_tech_fr

Would not help: you'd need 3 valid input clock-cycles before releasing DCM's reset (at least for Spartan3) - so knowing that you have 3 valid input clocks means, that you already know that the clock is valid.

Perhaps, you could build a statemachine: periodically reset the DCM for some ns and waiting for some ms for the DCM to lock (have a look at the datasheet for worst case timing) and re-apply a reset if DCM hasn't locked yet (but you would need a reference-clock for the statemachine)...

But if you have a reference-clock, you could use this clock for one counter that periodically resets a second counter driven by your input-clock: define your input clock as valid as soon (as long) as the second counter is within a specific boundary just before he sees the very next reset..

Hope, I didn't describe my idea too complex...

Cheers Jochen

Reply to
Jochen

This is easy if you have a continuously-running clock somewhere. If you don't, you can easily detect when the clock starts for the first time after power-on ( have the clock advance a 2-bit counter that you had reset during power-on.) But if you also want to detect if the clock has diappeared later on, you need some timing element somewhere. There is no mystery, it's all very logical, and your sharp Gallic analytical mind will understand that... Cheers Peter Alfke, Xilinx

Reply to
Peter Alfke

Much as Peter has said..

Two methods..

one is to run a second timer and compare results... you can get to ppm accuracy then provided you reference is accurate enough. We do this to check serial clocks against a 25 ppm reference.

Another is to use a simple RC filter on a couple of pins from the FPGA... note that it is important that the centre tap is connected by a C to the FPGA... so that if the FPGA remains inactive either high or low it will have no effect. I've also done this for a rough is the clock 16 MHz or not .. 8 Mhz turn on/off or there abouts .. not very accurate but it wasn't necessary.

Simon

Reply to
Simon Peacock

Hi,

there are a couple of general control signals for the DCM, i.e. STATUS[7:0], one of which STATUS[1], indicates if CLKIN is stopped.

I've never used this myself and I'm not sure if it will be of help to you but there's more details in the V2Pro platform handbook should you need it.

Good luck, Ben.

seb_tech_fr wrote:

Reply to
Ben G

Yes, it's a very good idea... if it works !! :lol

If only the DFS outputs are used (CLKFX & CLKFX180), this statu bit will not g

That means, I have to use the clock CLKFX or CLFX180 somewhere in m

design :

I will try .

Thanks everybody

I will give results in a few days..

Hi

to

you

a

cloc

wil

Reply to
seb_tech_fr

Hi Sebastien,

My reading of that would be that as long as you are not using CLKFX or CLKFX180 then it should work, i.e. use any of the DLL outputs such as CLKO.

You can check this but as above I would say it's the opposite to this.

Good luck, Ben.

Reply to
Ben G

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