clock cycle per Instructions

Hi all,

I am trying to calculate clock cycles per instructions by running the test cases and monitoring the waveforms.

I am confused to calculate the cycles for memory and IO related instructions...

For example MOV AL,33H ------>Took 3 clk cycles for my design OUT 32H,AL------>Fetching and decoding takes ----10 clock cycles write in to memory starts after three clock cycles of fetching and decoding process and ends after 1 clk ending of fetching and decoding cycles-- 8 clk cycles And execution takes----1 clk cycle... HLT

my question is should i have to consider overlapping time of writing into memory also for calculatimg clock cycle of OUT instructions??R i should subtract the writing time???

So OUT instruction takes 10+1= 11 clock cycles or 3+1=4 clk cycles..?? which is correct..??

regards, faz

Reply to
fazulu deen
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Code profiling is a complicated thing, and is definitely off-topic for a FPGA forum.

Perhaps your architecture is completely wrong if you need to profile th code that closely.

HTH!

Reply to
RCIngham

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