Hi,
this is my code
dcm1_1 : dcm1 port map ( CLKIN_IN => CLK, RST_IN => RESET, CLKFX_OUT => clk_20M, CLKIN_IBUFG_OUT => open, CLK0_OUT => clk_int, LOCKED_OUT => locked);
clk_div_1 : clk_div_262k port map ( CLK => CLK_20M, DIV_262144 => clk_led2);
I get this error there during synthesis: ERROR:Xst:2035 - Port has illegal connection. Port is connected to input buffer and following ports: Port C of instance cnt1_1/BU20 in unit cnt1_1 with type FDE
I have no idea where the problem is.
Is it generally a good idea to use the dcm and a clk_divider if a very slow frequency is needed? Or should I use only clk_dividers?
regards, Benjamin