If we design an S3-based system using an internal clock doubler, the design software wants to know our input frequency. In our case, we want to double the incoming 20 MHz clock to 40 MHz for internal use.
In other applications, the incoming clock may range from, say, 18 to
25 MHz, and we'd like to use the same FPGA design without recompiling. Looking at the Xapps and datasheets, it's implied that the clock doubler will double an incoming clock over the specified range (18 to 167 MHz in) without otherwise being "told" the nominal input frequency. Is that right?Thanks,
John