Hi all,
started to look into alternatives to Verilog and VHDL and stumbled over chisel from UCB:
Any experiences and comment on this language?
Looks like some challenge for me as it involves practically learning 3 new languages at once: chisel itself, Scala on which it is based, and Verilog, which is produced (I'm used to VHDL).
Cheers, Martin
PS: I was *very* long absent from this group ;-)