chipscope pro problem (par)

in

placed

just dont pay attention to that, it always gives zillion of similar warnings!

advice: if you do any serious FPGA verification (with Xilinx silicon) you

*MUST* use ChipScope - no way around it. There are other OCI solutions availabe of course also, but I would defenetly consider ChipScope as primary tool.

Antti

PS I am using ChipScope to to capture at 3GS/S :) with rocketIO and custom "analyzer" application, kinda nice to see 3GS/S Logic analyzer - my primary use was capturing USB HS raw data, V2Pro rocketio can be directly coupled to USB (receive only)...

Anyone looked at or using Synplicity's Identify product? Wanna share your experiences? Cheers, Syms.

Antti Lukats a écrit:

I still wonder why Xilinx is *selling* this tool, especially since you can't do much serious work without it. Altera's SignalTap is free and (IMO) much more user friendly.

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:) yes looked only shortly, its more like "rtl debugger" not logic analyzer. A nice tool in any case that for sure. Unfortunatly our free license expired before I had any chance to test any further. Its funny, they Identify lite is supposed to be free, but after registration they will try to call your mobile, and the free license expires very quickly.

Antti

you

primary

You are right - it would much nicer if ChipScope would be free (at least for those who have ISE full...) I got ChipScope initially as bundled software with ML300 (total value of purchase >$5000 USD), that CS was version 5.1 and there was no free update to even 5.2 !! That was bizarre! And the price went up 2 times what also isnt so nice change. I guess the reason Xilinx is selling ChipScope is that ChipScope cores, including ILA (not only ATC2) - are designed by Agilent, so there could be still some ownership issue. This information is (about who wrote ILA cores) is from inside Agilent so I assume its correct. Possible that also explains why the core integration isnt always working as smootly as it could be and why Xilinx still is struggling to get Chipscope analyzer to work in Linux.

I have used ChipScope for long time, and sure have a lot of struggle with it. Its getting better with every service pack. And if you KNOW it you can use it in very friendly manner. If you dont, well then you have to learn, possible the hard way.

I dont want to say that, but when I first time tested SignalTap - I was really surprised how easy it was! Funny thing is that I used SignalTap to check out how MicroBlaze works in Cyclone :) ok, YES, SignalTap is easy (its not directly free as you need use it on a PC that is required to be online and sends reports back to Altera), SignalTap doesnt have some features that I use in ChipScope VIO and core generator are not there.

Hm, another thing that is missing from ChipScope is upload of user memories! (SignalTap can do that).

ok, enough :) Antti PS I still have a dream of doing a cross platform OCI system some day (partial work is completed)

It is possible to do serious work without ChipScope or SignalTap, but it requires synchronous design and continuous simulation and regression testing.

-- Mike Treseler

you

Hi Mike,

I was already wondering who will reply and say that he can do all by simulations only :) Sure it is possible todo it all without the use of any OnChipInstrumentation tools at all.

But if you work with external ASIC PHY test chips without even having proper timing specs for those or in case the latency specs for the external phy chips are wrong, then well you just cant simulate what you do not know, you need to see whats happening inside the FPGA. Maybe my experiences are not common and everybody else are very happy with simulations only, but I have found ChipScope and its advanced use of very great value, and it has been able todo many things that would not be possible or would have taken too much time.

Like RocketIO has some gotchas, and the simulation models are not good enough, so by doing simulations only you can not get a Serial OOB detect circuitry working. No way. Because rocketio receives random noise with 4 bits repeating pattern when no valid signal is applied to RXP/RXN. This can only be found when catching the actual rocketio recived signal. Attaching ChipScope makes that all visible, you see the problem and you can write ip cores that take care of that, or if you want can write simulation models that the real behavior into account.

So I would say my statement says, if you are doing serias FPGA verification for a longer period of time, involving projects with latest technologies (both FPGA and outside components and circuitry) then the "on-chip" instrumentation use is a MUST, this is what I said. Sure there are many very serious project that can be completed very succesfully without ever using OCI.

As of CS vs SignalTap vs Identify - all are good tools, but I wish there would be something better. Something that is cross platform and more open in design - ChipScope doesnt not provide option for low clock or clock enable, or and well my wishlist is long. So long it might be easier todo by itself then attempting to use existing tools.

Antti

that's what i thought ...

VIO

primary

there

open in

enable,

itself

Did you check out DiaLite from Temento Systems

/daniel

thanks for the link, i'm checking it out right now ... thx...

. . .

...

Yes, specifying and modeling the interface is very important. But this is a job best done by the vendor of the chip.

I agree that logic design and simulation are useless until all interfaces are specified. I also understand that instrumentation of some sort is required for this task by the person doing it. But this alone does not validate the design on *my* side of the interface nor does it allow me to specify or model my design for use by others.

Using devices from vendors who supply full timing specs and simulation models makes it possible.

HDL simulation is like that.

-- Mike Treseler

Hi Antti-

FYI, in one of our more recent releases, we've added storage qualification (a more powerful kind of clock enable that you referred to) and ability to handle slow and stopped clocks (complete with the typical "Slow or stopped clock?" message that regular LA's give you).

It sounds like you've used OCI tools pretty extensively -- I'd be interested in hearing about your wishlist for OCI tools. For instance, what do you mean about cross-platform? Do you mean a combined SW/HW debug environment?

Also, how about the open design idea? Would you like to be able to design your own debug cores or modify existing ones?

In any case, we always like to hear from the experts, so keep the comments flowing!

Regards,

-Brad

Antti Lukats wrote:

Antti,

Let me clear a couple points you have brought up.

First, the original ChipScope Pro ILA, IBA and VIO cores, along with the Generator, Inserter and Analyzer tools were all developed entirely by Xilinx from the very beginning. The only collaboration with Agilent for deliverables within the ChipScope Pro toolset has been the development of the ILA/ATC and ATC2 cores, which has been shared nearly equally during our partnership. (Agilent, of course, has put a great deal of effort into their Trace Port Analyzer and the new FPGA Dynamic Probe tools.) The information you have received was incorrect.

Second, since the product's introduction in March 2000, the price has only gone up once, from $495 to $695, to account for a number of new cores and features. I can't speak for prices of integrated packages, but any increases have not been due to price changes of ChipScope Pro itself.

Third, ChipScope Pro is currently (version 6.3i) available for Linux platforms for Core Generation and Insertion, and expect to see Analyzer support soon.

Finally, we still charge for ChipScope Pro because we consider it a "value-added" product above and beyond the scope of the ISE toolset, like other tools like EDK, PlanAhead, and System Generator. It is not a required tool (even though you consider it a "*MUST* Have" -- thanks for the endorsement!), and I expect we will follow this model for forseeable future.

Thanks for you comments, David Dye Xilinx Technical Marketing Longmont, Colorado

Brad, Add at least one clock enable to the main capture clock. The problem with chipscope is it relies on the slowest part of the fabric, i.e. the BlockRams, to store the data. This means a lot of designs that run fast in rest of the fabric are too quick to be analysed with ChipScope. If chipscope had a (or maybe several) clock enable(s) it would be easy to get around this problem. e.g. Instantiate two chipscopes, enabled antti-phase. (Ho ho! Sorry Mr. Lukats! I see, reading back, you've suggested this too.) Cheers, Syms.

open in

enable,

itself

That would be great. I wouldn't mind contributing stuff back in, I'm sure that goes for a lot of folks. Best, Syms.

chipscope

this

Sorry

Hi Symon,

sorry I commented you on the other thread but Brad had it covered already.

YES, I have used ChipScope to capture on 4 phases eg doing internal clock resolution enhancement by a factor of 4, also I have used ChipScope to capture raw Data from RocketIO giving sample rate of 3GS/S, well that application required our custom replacement for the "ChipScope Analyzer".

Antti

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memories!

The information as I did explain was as correct as received from inside of Agilent, but I agree I could have understant it not 100% precise, I was told by Agilent that not only ATC but also ILA cores are from Agilent, possible they wanted to say "not only ATC2 but also ILA/ATC" are from Agilent.

I havent hopefully said that price has changed more than once (if I have then that must have been typo error from my side). If you have CS 5.1 but cant upgrage to 5.2 and are required to buy new version with new price? I still thing that updates at least between minor version should be free of charge.

without Analyzer there is no use for ChipScope. I did expect that Linux Analyzer will be available in 6.3 - I did know its coming..coming and it looked to me as it could come already in 6.3, a small disappointment that it did not make it into 6.3 release

ok, good this comment is not me, I havent said Chipscope should be free it was somebody else who indicated such a wish. hm that was somebody wondering why it isnt free.

uups I better watch what I am saying, I have said it would nice to have CS free for (at least) registered ISE users. Ok that stands, it would be nice. But hasnt have to be no problems with that. It could cost more if it would be more powerful.

Antti Lukats a écrit:

It was me wondering why it wasn't free when Altera's SignalTap was. Actually, I'm only using ISE WebPack (we don't do many Xilinx designs, we're more Altera-flavoured) so I'm not complaining too much :o)

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Hmmm, haven't you see the AOL commercials? We want it free too!

--

Rick "rickman" Collins

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removed.

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