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chipscope pro 6.3i clocking issue

but i have have this problem and think that a small change somewhere will fix it. i have been using xilinx system generator to design a neural network for FPGA. it seems to synthesize and download properly. i have added a chipscope cores to check if it runs as expected on the FPGA however it complains when run that it has a slow or stopped clock. i interpret this to mean that system generator has not correctly generated the VHDL file or i have missed a step somewhere. please any pointers you have for this problem are appreciated. I am using xilinx system generator, Ise and chipscope Pro version 6.3i with updated ip. the device i am developing for is the virtex 2 pro XCV2p50.

Reply to
wolf359mmcb
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Hi,

I ran into the same problem a few days ago. In my case the problem was that the ADC which provided the clock signal to the FPGA didn't get enough power. I.e. the FPGA didn't get any clock signal at all. Check your clock circuitry, is it working correctly?

regards johan

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Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
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Johan Bernspång

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