ChipScope Core Generator Flow

Hello,

I want to use the Xilinx Chipscope. As described I generated the controller and logic analyzer using the ChipScope Core Generator and than instantiated the icon and ila instances in my VHDL and synthesised it using Precision RTL. But the generated edif file does not contain any cell icon and ila. Therefore Chipscpoe logic isn't implemented and I can't use it.

What is my fault?

Regards

Thomas Reinemann

Reply to
Thomas Reinemann
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Could be that Precision RTL optimizes out the icon and ila instantiations. I've never used Precision RTL, but it should have a way (most synthesis tools do) to not optimize out certain blocks.

HTH, Jim snipped-for-privacy@yahoo.com

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Reply to
Jim Wu

Very true, for example you need this with Synplify

attribute syn_black_box : boolean; attribute syn_black_box of icon : component is TRUE; attribute syn_noprune : boolean; attribute syn_noprune of icon : component is TRUE;

HTH, Syms.

Reply to
Symon

For Precision one needs:

attribute preserve_driver : boolean; attribute preserve_driver of control0 : signal is true;

The Chipscope Core Generator generates attributes for the predecessor of Precision, Leonardo and I assumed they are compatible :-(.

Bye Tom

Reply to
Thomas Reinemann

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