Hello,
I want to use the Xilinx Chipscope. As described I generated the controller and logic analyzer using the ChipScope Core Generator and than instantiated the icon and ila instances in my VHDL and synthesised it using Precision RTL. But the generated edif file does not contain any cell icon and ila. Therefore Chipscpoe logic isn't implemented and I can't use it.
What is my fault?
Regards
Thomas Reinemann