Hi
I have an VHDL core that is sythesizeable with the following tools
Synopsys Design Compiler Cadence Encounter RTL Compiler
Until now I was using XST for sythesis and it seems when I try to run sythesis for the VHDL core with XST I get a bunch of errors. The convenient thing with Xilinx was the Chipscope which allows the on-chip debugging. So I wonder if the tools mentioned at the beginning also support this kind of on-ship debugging? Or could I sythesise the design with the ICON and ILA with the Synopsis or Cadence RTL compiler and then use CHIPscope. Does anyone have tried that?
Many thanks Philipp