Hi Xilinx Killers,
It is really annoying to rename and group all the signals everytime when design is modified and new bit file is used to configure the fpga. Anybody knows how to avoid renaming and regrouping signals in the analyzer when new bit file is loaded to FPGA?
And one more quick question, how to investigate state_reg of a FSM by using chipscope? Because the original name of the interesting state_reg is modified after synthesis, I dont't know which signal I should investigate now.
For Altera signaltapII, it is very easy to use for on-chip debugging. And it is very easy to learn too. Miss those days when using Quartus.
Thanks in advance for your input,
Sics