Changing refresh rate for DRAM while in operation?

On Oct 26, 8:05 am, Gabor wrote: []

I think you may be addressing his real problem as he mentions in another post.

On Oct 25, 7:31 pm, snipped-for-privacy@gmail.com wrote: []

I think your test is a difficult one since you are looking for failures due to discharge by random radiation effects. Slowing down the refresh and finding one or few cells that tend to discharge more quickly than the rest as a few others have suggested does not really apply to the problem.

You haven't specified what kind of radiation you are testing for (high energy cosmic rays, background radiation, BETA radiation, Nuclear power plant radiation(monitoring or robotic device?), or nuclear bomb) This is not a simple test rig. The programming of the refresh rate is a minor problem. The problem, if I understand your description correctly, is measure the failure rate DUE TO RADIATION versus refresh rate. Since radiation induced failures are random, you'll have to do a good number of test runs at various refresh rates to get a handle on the range of failure rate (to be able to say there were Y failures +/-y at refresh rate X) You need to be able to sort out what failures are due to the memory device itself and what is due to the radiation.

The supplier of your memory may be able to give some advice on this test setup. (or are you working for the memory manufacturer?) I think you do not need to change the refresh rate dynamically. You should be able to do test runs at a fixed refresh rate, get the failure rate, reboot with a new refresh rate and start again. Depending on the radiation source you may need to replace the memory modules in a controlled way, to deal with the cases of permanent damage by the radiation.

I'm not trying to be offensive with this final question/comment, but I take it your background is computer science only, right? You may need to get someone with a background in physical sciences (a physicist) to help design the experiment. (I have a BS in physics, but nuclear physics is not one of my strong points.)

HTH, Ed

Yes it will. The charge in the cell decreases over time. So running with a faster refresh rate will, at least somewhat, increase the minimum charge in a cell and increase the signal on the bit line.

Have you reviewed the literature on this? I can't believe that this type of experiment hasn't already been done.

del

If it is an up counter with a comparator, be careful: if it is an equality rather than a greater-than comparator, and the CPU sets the trigger value to less than the current value of the counter, then the counter will have to roll all the way over, and likely miss a refresh, with potential data loss resulting.

Andy

No, I'm looking at the retention. How does radiation effect the retention characteristics of the DRAM. As mentioned in another reply, it makes sense to change DRAM refresh rates at different temperatures. Does this help in a radiation environment?

We are using gammas for this test. Following students will use other radiation sources.

Not working for the mfg. I wish I was, then I'd have more resources. I'm working for a university (as in, I'm a student).

I have a nuclear engineer helping me with this. Actually, it's the other way around since this isn't really related to the deliverables for my thesis.

Actually that sounds like a good idea. I'll look into that, thanks.

-Eric

Jonathan Bromley wrote: (snip)

I have seen ATX style motherboards for PCs with built-in video that use a part of the main memory. I don't know how they do the access, though.

-- glen

Good point: if doing that, it's advisable to reset the counter (and issue a refresh) whenever you set the trigger value.

- Brian

I think it would be really tough to do what you want to do. The reason is that DRAM cell retention time charcteristics are not always deterministic. Some cells will retain data for hundreds of milliseconds, while other cells will retain data for tens of seconds, and they don't always stay in the "hundreds of millisecond" bit or the "tens of seconds" bin.

Ravi Venkatesan's paper has some numbers of DRAM cell retention time characteristics [Venkatesan2006].

What this paper doesn't talk about, and what will hurt you is the Variable Retention Time (VRT) characteristics of DRAM cells. That is, a given DRAM cell can retain data for tens of seconds most of the time, but once in a while, it can become a leaky cell that only retains data for tens of milliseconds. End users sometimes refer to this as being a "weak bit". [Yaney1987,Restle1992,Ueno1998,Mori2005,Kim2004]

Now, if you're trying to use the DRAM device as a SEU detector of some sort, it depends on how much radiation you expect. If there are a lot of radiation in your environment, then you don't need to do a lot of work beforehand to prepare your sample. If, however, you want to measure something that's very subtle, and maybe someone that would occur no more frequent than once per X minutes, then you'd really have to spend a couple of months with a DRAM device and a tester in a cave

50 feet below ground (need to make sure that there are no neutrons hitting the DRAM while you're characterising it), then characterise it to the level so that you'll be able say with some level of mathematical confidence that you know where all the weak bits in the DRAM device are.

Then, once you know what your device looks like, then you take it to the environment where you want to use it to measure your SEU rate, then you'd be able to (to some degree) distinguish between a cell that failed "early" because it has some built-in VRT characteristic, as opposed to a cell that failed because of a SEU.

Good luck David

@INPROCEEDINGS{Venkatesan2006, author = {Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg}, title = {Retention-Aware Placement in DRAM (RAPID):Software Methods for Quasi-Non-Volatile DRAM}, booktitle = {Proceedings of the 12th International Symposium on High Performance Computer Architecture}, year = {2006}, pages = {157-167}}

@INPROCEEDINGS{Yaney1987, author = {D. S. Yaney, C. Y. Lu, R. A. Kohler, M. J. Kelly, J. T. Nelson}, title = {A Meta-Stable Leakage Phenonmenon in DRAM Charge Storage - Variable Hold Time}, booktitle = {International Electron Devices Meeting Technical Digest}, year = {1987}, pages = {336-338}}

@INPROCEEDINGS{Restle1992, author = {P. J. Restle, J. W. Park, B. F. Lloyd}, title = {DRAM Variable Retention Time}, booktitle = {International Electron Devices Meeting Technical Digest}, year = {1992}, pages = {807-810}}

@INPROCEEDINGS{Ueno1998, author = {S. Ueno, T. Yamashita, H. Oda, S. Komori, Y. Inoue, T. Nishimura}, title = {Leakage Current Observation on Irregular Local Pn Junction Forming the Tail Distribution of DRAM Retention Time Characteristics}, booktitle = {International Electron Devices Meeting Technical Digest}, year = {1998}, pages = {153-156}}

@INPROCEEDINGS{Mori2005, author = {Yuki Mori, Kiyonori Ohyu, Kensuke Okonogi, Ren-ichi Yamada}, title = {The Origins of Variable Retention Time in DRAM}, booktitle = {International Electron Devices Meeting Technical Digest}, year = {2005}, pages = {1057-1060}}

@INPROCEEDINGS{Kim2004, author = {Y. I. Kim, K. H. Yang, W. S. Lee}, title = {Thermal Degradation of DRAM Retention Time: Characterization and Improving Techniques}, booktitle = {Proceedings of the 42nd Annual International Reliability Physics Symposium}, year = {2004}, pages = {667-668}}

The video and processor were synchronized to access memory on opposite clock cycles. In the mode that doubled the frequency some of the time, the controller (address decoder too) checked to see whether RAM was being accessed or not (as opposed to ROM or other resources), and if not RAM, the clock was doubled for that access (the 6809 was a completely static design, capable of even stopping the clock). We called that the "1.5x poke". The DRAM refresh was done separately by the controller in between video frames.

The always-doubled mode ("2x speed poke") doubled the processor clock regardless, and the video displayed the pixels for whatever memory the processor was accessing when those pixels were scanned. There were usually some binary counters visible on the screen, but most of it was random bits. In this mode the dram was not refreshed by the controller, so processor accesses had to do it, which like I mentioned, as long as the basic interpreter was running your code, would keep it alive.

Dang, that was a fun machine.. I think it is still in my attic somewhere.

Andy

You brought up some interesting points that I didn't know. I knew that different cells had different retention times but I was not aware there was variation in the same cell. That's definitely a problem...