Changing refresh rate for DRAM while in operation?

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Hi,

I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera
DE2 board. I've gotten the hardware interface squared away (thanks
everyone for your help!).

Now it's the tricky stuff. Any one have an idea how I can change the
refresh rate while the RAM is in operation?

I have the DRAM interface built using the SOPC builder that comes with
Quartus II using the NIOS II system.

I know you can change the refresh rate during the build but I need a
way to change the refresh rate during operation. The only thing I can
think of is maybe change the clock speed? I have it running off a
50Mhz clock....

Thanks,
Eric


Re: Changing refresh rate for DRAM while in operation?

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The most obvious question would be 'Why?'

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That will limit your options (as would probably most other vendor IP DRAM
controllers).

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A simpler way would be to simply have a DRAM controller that has an explicit
'Refresh Request' input that would cause the controller to perform a
refresh.  Then connect that input up to any programmable timer or other
logic that you would like to use.  Changing the clock rate would be far down
on my list of ways to accomplish your goal....but again, it begs the
original question about why you would want to change the refresh rate
dynamically at all.

KJ



Re: Changing refresh rate for DRAM while in operation?
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Assuming he has a good reason to change it,
the safest thing to do would be to call a
routine in flash to change it.



Re: Changing refresh rate for DRAM while in operation?

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Thanks for giving me the benefit of the doubt. I put this in another
reply, but the reason I want to change it is to characterize the DRAM
to get it's retention characteristics in a radiation environment. So I
want to know how long the DRAM keeps it's charge given a specific and
controlled environment.

Interfacing, programming, and DRAM definitely aren't my areas of study
(materials is). This is for a small but time consuming part of my
thesis project.

Thanks,
eric


Re: Changing refresh rate for DRAM while in operation?
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Why?



Re: Changing refresh rate for DRAM while in operation?
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Since the only purpose of the refresh circuitry is to avoid the
memory dropping bits, it should already be running at the slowest
possible rate, and speed reduction will be harmful, while speed
increase will do no good.  So this is not a good idea.

What are you trying to do?

--
 Chuck F (cbfalconer at maineline dot net)
   Available for consulting/temporary embedded and systems.
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Re: Changing refresh rate for DRAM while in operation?
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Although it's not expressed in DRAM specs and you wouldn't want to
rely on it, the effect of reducing refresh rate is to increase the
access time.  I'm not up-to-date with DRAM technology, but my
experience with devices 30 years ago was that you could turn off
refresh (and all other access) for 10s or more without losing the
contents, provided you weren't pushing the device to its access time
limits.

So, it's not impossible that reducing refresh rate would have a use
(albeit outside the published device spec).  But, as you suggest, it
would help if he would just tell us what he's trying to do.

Mike

Re: Changing refresh rate for DRAM while in operation?

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Although that may well be the case for asynchronous DRAMs (because the
reduced charge in the memory cell capacitor would mean that the sense
amplifier took longer to register the state), this would not be the case for
SDRAM since this registers the outputs a fixed number of clocks after the
access starts. If the underlying access time increased by too much then the
data would just be wrong.



Re: Changing refresh rate for DRAM while in operation?
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For certain addressing patterns, the refresh can be eliminated
alltogether, when the addressing sequence is such that all (used)
memory cells are naturally being read, and thus refreshed, within the
required time.
Peter Alfke


Re: Changing refresh rate for DRAM while in operation?
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Sinclair ZX?
at least some old Z80 homecomputers used refresh by video scan

Antti





Re: Changing refresh rate for DRAM while in operation?
On Wed, 24 Oct 2007 07:15:08 -0000,

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Yes, and it's a completely ridiculous way to do it.  The
added cost of making frequent additional row accesses is
far greater than the cost of the necessary refresh.

A DRAM row is effectively a cache.  When you access a row,
you read the whole row into the DRAM's row buffer as a free
side-effect, and can then make very fast column accesses
to anly location in the row.  It's preposterous to throw
away that massive free bandwidth just to save yourself
some refresh effort - unless you're trying to design
a $80 home computer/toy in the early 1980s.

In those days, the video buffer was a sufficiently
large fraction of the overall DRAM that it was
reasonable to lay out the video memory so that
every row was automatically visited by the video
scan, giving a refresh cycle every 20ms (16.7ms
in the USA).  That was out-of-spec for many DRAMs
of the day (8ms refresh cycle) but in practice it
worked in almost all cases - and the manufacturers
of those computers had a shoddy enough warranty
policy that they weren't going to worry about a
handful of customers complaining about occasional
mysterious memory corruption on a hot day.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Re: Changing refresh rate for DRAM while in operation?
Jonathan, why so aggressive?
I was just pointing out that certain applications naturally perform
sufficient refresh operations in their normal addressing sequence. I
can't see why this is "completely ridiculuous"...
Peter Alfke

wrote:
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Re: Changing refresh rate for DRAM while in operation?

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Ooh, I can be much more aggressive than that!  And it
certainly wasn't directed at you.

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Nor is it; the absurdity comes from bending the addressing
so that only a small part of each row is sequentially accessed,
thereby wasting the massive increase in memory bandwidth that
can be achieved for sequential-access applications by using
the row buffer as a cache.  My spleen was being vented at some
designers of old computers (as alluded to by Antti, not you)
who used video scan to access every row of DRAM on each video
field, thereby unnecessarily burning-up memory bandwidth
(which was in short enough supply on such machines) in order
to save the trouble of doing refresh properly...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Re: Changing refresh rate for DRAM while in operation?
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The bandwidth is there for the designer to use how they wish.
It also only actually matters, if that bandwidth is the
bottleneck in the total design.

eg I have done designs using interleaved video access, which removes
flicker, and makes the system appear to be dual-port.
On your yardstick, because the bandwidth is not 100% used, this
is a bad design ?

-jg


Re: Changing refresh rate for DRAM while in operation?

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And by not having to perform explicit refreshes, the bandwidth is
slightly higher and latency is more predictable.  If your application is
one that always addresses all the memory that it uses (no need to
refresh rows you are not using) within the minimum refresh interval,
then this can sometimes be used to simplify the system.  There are still
plenty of FPGA applications that, for example, use the DRAM only for a
video frame buffer.

Re: Changing refresh rate for DRAM while in operation?
(snip)

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Processor speed has increased somewhat faster than DRAM speed.

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When RAM cycle time was faster than processor cycle time.

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Any access to the row will refresh the whole row.
If you address it such that sequential characters are
in different rows then it is refreshed much faster than
the frame rate.

-- glen


Re: Changing refresh rate for DRAM while in operation?
On Wed, 24 Oct 2007 13:06:34 -0800,

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Indeed so; a fair point.  And you could perhaps also argue
that the cost of row access, as a fraction of a data access,
has increased quite dramatically over that time.

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That too is an interesting point.  My own experience of
that sort of video controller was that they typically
caused lots of processor stalling while video data
was being fetched, but it may have been different
for other designs.

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True, but then you are *really* wasting bandwidth
by doing more row accesses than necessary.

I guess you could, by juggling the use of address bits
sufficiently cunningly, arrange that row accesses by
video scan would *just* provide enough refresh to
satisfy the data sheet spec.

I've seen many different variants on this: block refresh
during frame blanking, for example.  They all seemed
pretty unpleasant to me at the time, and still seem so
now - although, of course, no-one needs to do that sort
of dirty trick any more (do they? please?)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Re: Changing refresh rate for DRAM while in operation?
(snip)

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I have seen ATX style motherboards for PCs with built-in
video that use a part of the main memory.  I don't know how they
do the access, though.

-- glen


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If I recall, the Apple II also refreshed its RAM this way, too.
-Dave Pollum


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The TRS-80 Color Computer (Moto 6809 based) refreshed during the
vertical retrace. But there was a bit in the system controller that
could be set to turn it and video access off, while doubling the
processor clock. As long as your Basic code was running, and not
waiting on a keyboard input or other event, the ROM interpreter's RAM
accesses managed to keep the RAM (at least the part of it being used)
refreshed. But if/when the code hit an error (and thus waited for user
response) you could watch the screen go from random pixels to all
white. Once the coding errors were eliminated, it was a reliable way
to double the processing speed when you did not need video.

Ah the good old days... but, I digress.

Andy


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