I am getting the below error when i perform a post layout simulation from Xilinx using Modelsim. I am sure the $width problem has been discussed in this forum before. But i was wondering why Modelsim looks for the X_LATCHE in the C directory when I have installed them in D. I was wondering where and how to change it.
# ** Error: C:/XILINX/verilog/src/simprims/X_LATCHE.v(48): $width( posedge SET:211374 ps, :211864 ps, 1570 ps ); # Time: 211864 ps Iteration: 2 Instance: /tb/dpackt/correlator_packet_detected_5242
Thank you in advance.