Changing clock domain

Hi,

following question:

I have a signal in an 48MHz clock domain, it is high for exactly one clock cycle. Now I want to pass it to an 90MHz clock domain where the synchronized signal should also be high for one 90MHz clock cycle. Is the following approach reasonable?

signal l_valid_48 : std_logic; -- high for one 48MHz clock cycle signal l_valid_h1 : std_logic; signal l_valid_h2 : std_logic; signal l_valid_h3 : std_logic; signal l_valid_90 : std_logic; -- should be high for one 90MHz clock cycle

process(Reset, Clk_90) begin if Reset='1' then l_valid_h1

Reply to
ALuPin
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The 3 FF approach is a good one, but you should create the i_valid_90 on the clock as well. Just put the combinatorial statements within your clocked process, and I think it should work just fine.

Regards,

Pieter Hulshoff

Reply to
Pieter Hulshoff

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