Hi,
I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner in a fpga. Fpga has a 27 MHz clock with which takes data from the tuner and serializes them to ASI. The serialization works well simulating a Null Packet as input.
Now I have to take data from the tuner with unknown clock. I had thought of a async FIFO. The clock of the tuner to the left of fifo, to the right my clock. Checking the level of fifo and inserting Null packet if necessary.
But how can clocking the fifo directly by the tuner without problems ?
Do you have an example of VHDL code that I could use ?
Thanks.
Kappa.