Hi, I want to test what kind of delay is introduced by having an input go through 1000 LUT1 primitive in a Spartan3E FPGA. I am using ISE 9.1 to synthesize this but during map, it seems that it is optimizing the LUTs out although these were instantiated as primitives. Is there any way to force ISE to keep these. The design is as follows:
library IEEE; use IEEE.STD_LOGIC_1164.all;Thanks, Amish-- Synthesis TRANSLATE_OFF library SPARTAN3E; use SPARTAN3E.VPKG.all; use SPARTAN3E.VCOMPONENTS.all;
-- Synthesis TRANSLATE_ON
entity delay_luts is port( input : in STD_LOGIC; output : out STD_LOGIC ); end delay_luts;
--}} End of automatically maintained section
architecture delay_luts of delay_luts is
CONSTANT number_of_delay : INTEGER := 1000; component LUT1 is generic(INIT : bit_vector := X"0");
port( O : out std_ulogic; I0 : in std_ulogic); end component;
signal internal_signal : STD_LOGIC_VECTOR(number_of_delay-1 downto 0); begin delay_element_first : LUT1 generic map(INIT => X"2") port map( O => internal_signal(0), I0 => input );
-- enter your statements here -- delay : for N in 0 to number_of_delay-2 GENERATE delay_element_middle : LUT1 generic map(INIT => X"2") port map( O => internal_signal(N+1), I0 => internal_signal(N) ); end GENERATE delay;
delay_element_last : LUT1 generic map(INIT => X"2") port map( O => output, I0 => internal_signal(number_of_delay-1) ); end delay_luts;