Celoxica DK1 to Xilinx Spartan II

Hello, I have written a program to run on the Celoxica RC100 board and compiled it to edif file. When i use the Xilinx Design Manager to convert it to a bit file, it always fail during the mapping stage saying it cannot fit into the device. I have tried many optimzation method in the DK1 suite and nothing works. Tried using its technology mapper (take very long to compiler) also cannot work. And it always exceed the maximum slices and 4 i/p look-up table (both exceed by 50%). I have tried the -r option in the mapping and it still exceed.

I'm using the following software, Celoxica DK1 Design Suite 1.1 Service Pack 1, compiler version 3.1.2676 Xilinx Design Manager Revlease version 3.3.08i, application version D.27

Thanks you from Triax

board and compiled

convert it to a bit

fit into the

nothing works.

compiler) also cannot

table (both exceed

still exceed.

version 3.1.2676

application version D.27

If you target EDIF, you can get a report on the area and timing of your design. You have to enable Generate Estimation Info on the Linker tab in your project settings.

This should help you track down which parts of your design take most area, and concentrate on optimizing those.

Of course you may find that your design cannot fit in the Spartan II on the RC100 board, in which case you will either have to simplify your design, or use a different board,

regards

Alan

-- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.