Celoxica DK1 to Xilinx Spartan II

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Hello,
    I have written a program to run on the Celoxica RC100 board and compiled
it to edif file. When i use the Xilinx Design Manager to convert it to a bit
file,
it always fail during the mapping stage saying it cannot fit into the
device.
I have tried many optimzation method in the DK1 suite and nothing works.
Tried using its technology mapper (take very long to compiler) also cannot
work.
And it always exceed the maximum slices and 4 i/p look-up table (both exceed
by 50%). I have tried the -r option in the mapping and it still exceed.

I'm using the following software,
Celoxica DK1 Design Suite 1.1 Service Pack 1, compiler version 3.1.2676
Xilinx Design Manager Revlease version 3.3.08i,  application version D.27

Thanks you
    from Triax



Re: Celoxica DK1 to Xilinx Spartan II
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board and compiled
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convert it to a bit
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fit into the
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nothing works.
compiler) also cannot
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table (both exceed
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still exceed.
version 3.1.2676
application version D.27
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If you target EDIF, you can get a report on
the area and timing of your design. You have to
enable Generate Estimation Info on the Linker
tab in your project settings.

This should help you track down which parts of your
design take most area, and concentrate on optimizing
those.

Of course you may find that your design cannot fit in
the Spartan II on the RC100 board, in which case you will
either have to simplify your design, or use a different
board,

regards

Alan

--
Alan Fitch
Consultant

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