Guys, In a recent thread here on VAF we learnt, more or less, that a large part of the Virtex-4's Cpin of 10pF is due to the large output FETs needed to drive HSTL IV at 48ma.
Does the CCLK pin have this problem? If not, where do I obtain an IBIS model representative of the CCLK input?
UG071 recommends simulating CCLK as an "LVCMOS_P12" which doesn't exist in the IBIS file. Of course all the other models include the "Cpin of death". Thanks, Syms.
CAF not VAF. Soz.
Symon,
The ISE software will create a pin specific IBIS model for your design.
Aust> Guys,
Hi Austin, Thanks, but I don't think that works for the CCLK pin on V4 which is used to clock configuration data into the device. (CCLK can't be used as general I/O AFAIK.) Thanks, Symon.
Symon,
I am not sure why that would not work, as even the dedicated pins have IBIS models, and the software knows about the dedicated pins, and thus should write out models for them as well.
The CCLK pin is a dedicated pin, and it can be both an input, and an output, so it is a normal IO cell, just like all the others, except that its programming is not an option from the bitstream, but set by its function as the CCLK pin (either a LVCMOS input, or a LVCMOS output). So its capacitance will be the nominal 8pF or so in V4 of any IOB pin.
Since we like to use identical cells, there would be no reason to go in hack off the unused bits just because it is a CCLK pin, and then require a different ESD protection scheme, and more testing later ...
Aust>> Symon,
OK, I understand, it all makes sense now! Thanks, Syms.
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