Hi,
I'm interfacing Micron's DDR with PowerPC using OPB DDR SDRAM controller available in EDK.
The problem I face in simulation is that during a single read operation CAS signal extends to two full (consecutive) clock cycles.
Thus for a burst length 2, I get 2 back to back identical burts.
However During single write the CAS signal is asserted properly for 1 clk cycle.
The DDR I use is micron mt46v16m16. I have tried with both 7.1 and 8.1 versions of EDK.
Can anybody suggest me the possible reason for this problem?