CardBus prototype in FPGA

Dear newsgroup,

I am quite new to FPGAs but experienced enough in digital ASIC design (VHDL, Verilog & stuff). Recently, we encountered some problems with the selection of the best FPGA for a design we are attempting. The design in question is a custom CardBus module, for which we are considering a Cyclone FPGA from Altera. The functionality of the module is not too complex. Beside the bus-related requirements themselves (CIS, ConfigSpace), we also need a FIFO. The bigger the FIFO, the better. Is Cyclone an appropriate choice for this application, or are there better solutions out there? Another issue is the time necessary for the FPGA to load its configuration, which can be as high as a couple of seconds. As far as I read in an earlier discussion on the newsgroup, this might be a big problem since the system software will power down the socket after seeing that the card does not respond within a short interval after insertion (less than 1 sec). Is there any reliable solution to this problem? If not, I am afraid the only choice is to try with the flash-based FPGAs from Actel, which does not come in too handy. I don't like the idea of paying for the Actel software, which is not even that good like ISE or Quartus. And the Actel parts seem to be much too expensive and difficult to program.

Looking forward to any suggestion,

Michael

Reply to
Michael
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(VHDL,

selection of

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need

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It depends entirely on the requirements of the FIFO, such as size, speed, latency, cost, component size, etc.

configuration,

earlier

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reliable

Smaller FPGAs normally load their configuration faster, although I don't have figures for any particular FPGAs. You might also consider using a PLD in the mixture, holding critical functions alive until the FPGA comes on line.

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Actel

Reply to
David Brown

Hi,

I am sure you could implement this in many different devices. Your job is to pick the best one for your design.

PCI 2.3, using 3.3v I/O, is very similar to Cardbus. For example, you can use the Xilinx PCI LogiCORE to implement a Cardbus design. I have seen it done.

A significant difference between Cardbus and PCI is that PCI provides a 100 ms time window for you to get the device in order before reset deasserts, and then some additional time (large number of cycles) before the first allowed configuration access. Cardbus does not provide as much time.

Your concern is legitimate, however you can certainly take steps to minimize any potential issue. Use a parallel configuration mode if available, and in any case use a high configuration clock rate. Use an FPGA with a small bitstream, like a 2s30. You can implement the Xilinx PCI LogiCORE in a 2s30, it has embedded memory with which you could implement a FIFO.

If you want to write your own Cardbus interface, you might consider usinig a moderate sized CPLD, instead of an FPGA, but in this case you'll probably end up with an external memory device to serve as your FIFO.

Eric

Reply to
Eric Crabill

mike writes

You should look at Lattice XPGA - this is an EECMOS/SRAM device - boots up

Reply to
Mikeandmax

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