Cardbus Power On Reset !!!!!!!!

snipped-for-privacy@gmail.com schrieb:

NO

this time is vendor dependant

Antti

Could you tell me what is the time according to cardbus specification, that CRST# must be asserted.

Do you not think it's about time you got hold of the relevent specs for what you're trying to build?

Nial.

Nial Stewart schrieb:

good point, but the time after power supply ramps up and the system asserts CRST first time is not in the specs and can not be as it depends on the host system. and very likely the CRST may occour several times during boot (similarly as PCI RESET does) so there is no answer.

the OP wants to know if the slow FPGA configuration time is ok, ie if the FPGA has time to configure before CRST, but there is no way of telling that time. To be on safe side one should assume that CRST could come as early as say 20ms after power good. I dont see any restriction for such short delay. In real systems it is more likely longer, but no specs on minimum time.

Antti

So does that mean CRST# could be asserted atleast 20ms , which gives enough time for FPGA to get configured?

snipped-for-privacy@gmail.com schrieb:

means nothing. the time after power good to first time CRST asserted can be from 20ms (or maybe less) to 20,000 years.

short you can not count that FPGA can configure before CRST asserted, depends on the config method and bitstream size etc

Antti

There is a (in the spec for cardbus) well documented method for extending the res delay, to get enough time for fpga initialisation. Read more detailled. One pin should be tied low, and one can hold recognition proces long enough.

res delay, to get enough time for fpga initialisation. Read more detailled. One pin should be tied low, and one can hold recognition proces long enough.

Thanks for the information.Could you please tell me how to obtain the spec for cardbus.Do I need PCMCIA membership for the same?