The "waiting for clock" status indicates that your acquisition clock is not active. As other posters indicated, you should check that your acquisition clock is active and specified correctly in your SignalTap II file. You can select your acquisition clock by browsing to your clock input from the Signal Configuration Pane of the SignalTap II file (.stp).
When the acquisition clock is active and the trigger condition is met, the status of the ELA changes to "Acquiring post-trigger data", indicating that the Embedded Logic Analyzer (ELA) is acquiring data and filling your circular buffer. When the buffer is full, the status will change to "Offloading acquired data" and then to "Ready to acquire". So I don't think you're overwriting your own data, as your first post asked.
When you say you reset the device, what do you mean? Toggling a reset signal on your logic that enables a gated clock would be strange, and I'd recommend you switch to using a non-gated clock for your acquisition clock. If you are asserting the DEVCLRn pin to do a hardware reset of the device, you will have trouble. DEVCLRn clears all registers in the device including the ELA registers. When the ELA registers are cleared, the SignalTap II file will not display the correct status until you re-run the analysis by choosing Stop Analysis followed by Run Analysis (Processing menu).
It seems most likely that your acquisition clock is incorrectly set in the SignalTap II file (.stp), or has strange logic on the clock path, given your recent posting. Hence cleaning up this clock / using another clock would be a good idea.
For more info and details, see the SignalTap chapter of the Quartus reference manual at
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Hope this helps,
Vaughn
Altera
[v b e t z (at) altera.com]