"Cannot synthesize logic..." ERROR

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Hi,

I am trying to synthesize hardware which changes one values in a
register array at rising and falling edge of the clock. Basically I am
trying to synchronize different actions on different edges of the clock
and write, for example, signal1 to reg(1)(31 downto 0) and signal2 to
reg(2)(31 downto 0). The line with *** gives an error.

if reset='1' then
   -- initialization of reg
***elsif rising_edge(clock) and (write_flag = '1') then
   reg(CONV_INTEGER(unsigned(reg_address1))) <= signal1;
elsif falling_edge(clk) and (write_flag = '1') then
   reg(CONV_INTEGER(unsigned(reg_address2))) <= signal2;
end if;

QUARTUS II 5.0 gives me the following error during compilation: "Cannot
synthesize logic for reg because its value changes on both rising and
falling clock edges".

What should I do?
If it's possible, I would like to keep rising and falling edge
clocking.

Thank you


Re: "Cannot synthesize logic..." ERROR
I think the problem happens due to to the same register being clocked
by different events - that's what the compiler does not like.
What would you suggest ?

I think maybe to have another process which sets RISING_FLAG to 1 at
rising edge and FALLING_FLAG to 1 at falling edge. Then make my other
process sensitive to the flags instead of clock.

process(clock, reset)
begin
   if reset = '1' then
      --reset flags
   elsif rising_edge(clock) then
      RISING_FLAG <= '1';
   else
      RISING_FLAG <= '0';
   end if;
end process;

-- SeCOND PROCESS that changes FALLING_FLAG in the similar way.


I am not sure if it'll work and be stable.. because not sure how long
the flag will stay at one and will it be enough to trigger the main
process.


Re: "Cannot synthesize logic..." ERROR

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The FPGA (and most of the world) doesn't have flip flops that clock on
both edges, so what hardware do you expect the synthesizer to map to?
You should not use a synthesis tool if you don't understand what the
hardware will look like.

Anyway, one possible fix would be to generate a double-rate clock with
a PLL (Are you using Stratix?).  Then you can clock everything on
rising edge but use enables on alternating clocks to act like your
code.  Oh, you also have a typo - you have rising_edge(clock) but
falling_edge(clk), so it thinks you have two different clocks.

 David


Re: "Cannot synthesize logic..." ERROR
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You could try using a DDR type register, if available in your target
device.  Not sure if they can be inferred or whether they'd have to be
explicitly instanced.  I'd say most probably the latter...

That does sound like what you're after, though I'm not sure how the
synthesis would handle to two different signal assignments to it, I
guess it could use multiplexers though I wonder about setup and/or hold
timings in this situation.

Re: "Cannot synthesize logic..." ERROR
Thank you, I'll think how I should go around it

To test this code, I am using a lower-end cheap and old FPGA (apex II).


Re: "Cannot synthesize logic..." ERROR
Thank you, I'll think how I should go around it

To test this code, I am using a lower-end cheap and old FPGA (apex II).


Re: "Cannot synthesize logic..." ERROR

Quoted text here. Click to load it

How about using two separate 32-bit registers, reg1 and reg2, instead
of reg(1) and reg(2).  You need to use 2 processes.  The process for
reg1 would use the rising edge of the clock, and the process for reg2
would use the falling edge of the clock.

-Dave


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