Cannot pass par in tcl, Xilinx webpack 9.1.

Hi, I am learning tcl in Xilinx 9.1. For the learning example watchvhd, the following error occurs.

ERROR:Portability:90 - Command line error: Switch "-intstyle" is excluded or already used.

What's wrong with it?

But for my slow laptop, which installed a 8.2 version ISE, it can pass the implementation. Could you help me out? Thanks in advance.

# open the project and set project-level properties project open watchvhd.ise project set family Virtex2P project set device xc2vp2 project set package fg256 project set speed -7 # add all the source HDLs and ucf #xfile add stopwatch.vhd statmatch.vhd cnt60.vhd dcm1.vhd decode.vhd #xfile add tenths.vhd hex2led #xfile add watchvhd.ucf # define all partitions #partition new /stopwatch/MACHINE #partition new /stopwatch/Inst_dcm1 #partition new /stopwatch/XCOUNTER #partition new /stopwatch/decoder #partition new /stopwatch/sixty #partition new /stopwatch/lsbled #partition new /stopwatch/msbled # get partition properties set props [partition properties] puts "Partition Properties : $props" # get top set top [project get top]

# get project properties available set props2 [project properties] puts "Project Properties for top-level module $top $props2" # inspect the current value for the following batch application options #set map_guide_mode [project get "MAP Guide Mode"] #puts "MAP Guide Mode = $map_guide_mode" #set par_guide_mode [project get "PAR Guide Mode"] #puts "PAR Guide Mode = $par_guide_mode" # set batch application options : # 1. set synthesis optimization goal to speed # 2. ignore any LOCs in ngdbuild # 3. perform timing-driven packing # 4. use the highest par effort level # 5. set the par extra effort level # 6. pass "-instyle xflow" to the par command-line # 7. generate a verbose report from trce # 8. create the IEEE 1532 file during bitgen

project set "Optimization Goal" "Speed" #project set "Hierarchy Separator" / project set "Use LOC Constraints" "false" project set "Perform Timing-Driven Packing and Placement" "TRUE" project set "Place & Route Effort Level (Overall)" "High" project set "Extra Effort (Highest PAR level only)" "Continue on Impossible" project set "Other Place & Route Command Line Options" "-intstyle silent" project set "Report Type" "Verbose Report" project set "Create IEEE 1532 Configuration File" "TRUE" # run the entire xst-to-trce flow process run "Implement Design" # close project project close

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