Can't get Quartus to Infer Dual Port Ram for Stratix2GX

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How do I get Quartus to infer a dual port RAM? I've tried a couple of
coding styles neither worked. I've also tried putting a
/* syn_ramstyle = "M4K" */ on the module statement and on the ram
declaration, that didn't help either. I've also tried the /* syn_ramstyle
= "no_rw_check" */ attribute.

The Quartus manual claims that it can infer a dual port, I'm using
version 7.2.

The first is from the Quartus Manual, the second is
   reg [WIDTH-1:0]       a_ram;
   reg [WIDTH-1:0]       b_ram;
   reg [WIDTH-1:0]       ram[DEPTH-1:0] /* syn_ramstyle = "M4K" */;

   always@(posedge sysclk) begin
      if(a_wrt) begin
     ram[a_addr] <= a_din;
     a_ram <= a_din;
      end
      else begin
     a_ram <= ram[a_addr];
      end // else: !if(a_wrt)

      if(b_wrt) begin
     ram[b_addr] <= b_din;
     b_ram <= b_din;
      end
      else begin
     b_ram <= ram[b_addr];
      end // else: !if(b_wrt)


      if(a_ld) a_q <= a_ram;
      if(b_ld) b_q <= b_ram;
      
   end // always@ (posedge sysclk)
  
The second is in the Xilinx style,
   wire [WIDTH-1:0]       a_ram;
   wire [WIDTH-1:0]       b_ram;
   reg [WIDTH-1:0]       ram[DEPTH-1:0] /* syn_ramstyle = "M4K" */;

   reg [ADDR_WIDTH-1:0]   a_indx;
   reg [ADDR_WIDTH-1:0]   b_indx;

   assign           a_ram = ram[a_indx];
   assign           b_ram = ram[b_indx];

   always@(posedge sysclk) begin
      if(a_wrt) begin
     ram[a_addr] <= a_din;
      end

      if(b_wrt) begin
     ram[b_addr] <= b_din;
      end

      a_indx <= a_addr;
      b_indx <= b_addr;
      
      if(a_ld) a_q <= a_ram;
      if(b_ld) b_q <= b_ram;
      
   end

Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
I finally gave up on inferring RAM blocks - the synthesizer is just
too fiddle. However, if you still want to try, use the templates.
You'll find them under the Edit menu.

Good luck,
Tommy

Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX

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I managed to make it work but it's incredibly sensitive. The two ports
have to be in different always blocks even though they share the same
clock. Also there doesn't seem to be a way to put a clock enable on the
read. I put in a work around that saves the address in a register and
then selects it if there is no clock enable but that's a kludge that
wastes logic and will slow down the address path. Altera needs to fix
this.

   assign           a_adr = a_ce ? a_addr : a_indx;
   assign           b_adr = b_ce ? b_addr : b_indx;
  
  
   always@(posedge sysclk) begin
      if(a_wrt && a_ce) begin
     ram[a_adr] <= a_din;
     a_ram <= a_din;
      end
      else begin
     a_ram <= ram[a_adr];
      end // else: !if(a_wrt)

      if(a_ce) a_indx <= a_addr;
      
      if(a_ld) a_q <= a_ram;
      
   end // always@ (posedge sysclk)
  
   always@(posedge sysclk) begin
      if(b_wrt && b_ce) begin
     ram[b_adr] <= b_din;
     b_ram <= b_din;
      end
      else begin
     b_ram <= ram[b_adr];
      end // else: !if(b_wrt)
      
      if(b_ce) b_indx <= b_addr;

      if(b_ld) b_q <= b_ram;

   end // always@ (posedge sysclk)

Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
is there a reason why not use the mega wizzard?
I have a Stratix II GX running with various DP-RAMs.

Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX
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I suspect that the O/P was trying to avoid having technology-dependent RT
files and hence aid reuse. However, it looks like the synthesis tools wil
thwart his worthy aim!



Re: Can't get Quartus to Infer Dual Port Ram for Stratix2GX

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You are absolutely right. I try to make my cores as technology
independent as possible. I have customers using them in both Xilinx and
Altera FPGAs as well as in ASICs. Even if you are staying with one vendor
you still want portable code if possible because the vendors make major
changes in their architectures. This particular design was done for the
Virtex2P, migrated to the Virtex4FX and then to the Stratix2GX. It will
eventually be in the Virtex5FX and the next Stratix than has SerDes (I
don't know if that will be Stratix3GX or Stratix4GX, I've heard that
Altera is skipping the Stratix3GX). Having to directly instantiate
components complicates things. It also makes designs messier because you
need a couple of levels of wrappers, the wrapper that the wizard
generates and a wrapper around that which makes it generic. It also means
that you have to do additional simulation because you have to run your
testbench on each variant.

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