Can multiple Ferrite Beads be used to connect ...?

...a lot of excellent advice! No much to add from me, the SGSSGS stack up suggested by John would be my favourite also.

BTW., I like to include ground vias next to where signals via from layer 1 to layer 6. (In fact whenever the signal's reference plane changes.) This reduces the loop area for the current travelling in the trace. Remember, the signal in this case will go from being referred to one ground plane to being referred to the other. The ground via makes sure there is a current path where this swap happens. Thinking as if single ended signals are actually differential signals, one side of which just happens to be ground helps make this clearer. Here's an article I found online that explains this.

As John says, there are many ways to make an acceptable board. The advantage of the SGSSGS stack up is that it's very unlikely to have problems. It may not be optimal depending on your system requirements, but it'll work well, especially with a liberal sprinkling of ground vias. John Larkin (who regularly posts here) has a different approach to his boards with more power planes that, as he's fond of reminding us ;-), work very well for his products. "We use one ground plane, between the power planes, maybe 3=power,

4=gnd, 5=power." My thoughts are that if there are splits in any of the power planes, you have to be careful with signal routing. John L is clearly expert so can avoid traps that somebody at the start of their design career might fall into. The SGSSGS setup allows you to route with gay abandon! Cheers, Syms.

Very interesting thread ;)

I'm trying to apply all this data to my design. OK, so I have a FPGA module which will be connected to a motherboard via a connector, which also provides the power supply. It's a Hirose 100 pin connector ; I dedicate 25 pins to ground so both boards will have good ground plane continuity.

However, the +3.3V power supply also comes through this connector, so I made a little drawing of the two options, with or without choke on the main power supply. It appears I need to put a choke if I don't want my power supply to act as a return path ; this would be problematic since the power supply has much less pins on the connector than ground.

So, I put a choke.

The end result is this :

I use 4 layers : Signal Ground Power Signal. Ground plane is over the entire board (except RJ45 and mounting holes), and is not shown. Power planes are in yellow : the largest one is the +3.3V ; the small one (bottom left) is the supply for the analog part of the LAN chip. Anyway, I tried to contour the power plane so that the decoupling caps between GND and +3.3V are on the edge of the plane, so signals exiting the module will have their return path either through GND plane or through the decap. I put a choke to block off the VCC that comes through the connector from becoming a return path.

How does it look ? I'd like this thing to radiate as little EMI as I can manage...

The drawing shows chokes on both sides of the connector. Only one choke (or simple ferrite) should be needed.

I'm not sure where the signals are on your board relative to the power pour and ground layer. When vias swap your signal between signal layers, your EMI will be affected by the distance to the closest capacitors, through the cap to the ground plane, and back to your signal. The closer the caps are, the better. If your signals are referenced to the far ground plane then pass over the power pour, the reference to ground is lost and the return current path needs to find a capacitor path (including very minor power-to-ground plane capacitance) between ground and the new power reference. If any of those signals are pristine analog signals, there will be crosstalk with other signals through the shared current path through the decoupling.

It's hard to tell what you're doing with the regulated supply as well. It looks like you have plenty of capacitors, but you need to make sure that the overall capacitance will stand up to your largest current step over the frequency range blocked by the choke. If you have circuits with rather steady draw, capacitors aren't much of an issue; if you slew amps at one clock edge, the situation is very different. Only you can know what your power levels may do.

It's a small enough board (small enough return paths) that EMI probably wouldn't be a major concern even with any reference crossings. The bigger issue may be if you have the need for some pristine analog signals that must be kept free of crosstalk.

It looks like it was a fun to do. Are you hand assembling this? If not, you may want to reconsider those few passive components that are at an angle. If you're hand soldering it, who cares?

Also - beware of vias that might be awfully close to the metal shield of your PULSEJACK since you could inadvertently short the case to an unexpected plane or signal.

- John_H

Yes, actually the drawing shows an IC on the "motherboard" and an IC on the module, both being powered from the same power supply, and both IC's having their own choke (a bit extreme, it was for the example).

Like this :

- signal (top layer) - prepreg - ground plane - FR4 core - power plane - prepreg - signal (bottom layer)

Actually, I don't think there is any other way with 4 layers considering components have to be put on the board (!) and I'll use no BGA here, the signal layers have to be outside...

I may then add a decoupling cap in the middle of my cluster of vias where the bus changes layers, to reduce the loops.

No analog in this board (it will be on the other side of the connector) except the ethernet chip... I am just concerned about this board emitting enough crap that it may affect the analog circuits on the "mainboard"...

I'll rethink this one.

I also tried to keep the signal paths as short as possible, mostly between SDRAM, FPGA and MAC chip. The SDRAM will probably run at 50 MHz which shouldn't pose problems.

Yes !!

Yeah, I'll build one or two for starters, so I can rotate my resistors ;)

Good one !!! I'll correct this ! Thanks !

Heh. I noticed the ethernet chip has at least 20 no-connect pins (since I use its internal PHY I don't need the external PHY pins), deleted the pads in the footprint, which left enough room to route the entire bus from this chip to the FPGA with zero vias, then simplified the layout, removed the vias on the clock lines, etc. This certainly is a hack ;) but it'll work. I like that ;)

Now if only DigiKey hadn't one month of lead time on the FPGA !! Argh.

Thank you John; Thank you Symon.

Its helpful!

Leon,

I read this thread with great interest and have a very closely related question.

As of May 07 Altera recommend putting their pll gnd pins in a split plane. The arguments in this thread make a lot of sense for seperate analog circuits being on the same plane because one can physically seperate them, but how about pll gnds which are 3mm (3 balls) away from a standard GND pin.

Any advice appreciated as this will end an argument in our office.

Colin