Can multiple Ferrite Beads be used to connect ...?

'commone',

What is it that you are trying to do?

I will assume since you posted here, that this is a FPGA question.

For the FPGA, the only time a 'single point' fed plane, or planelet (small plane) is suggested is with the MGTs (multi-gigabit transceivers).

For the MGTs, it is best to follow the MGT User's Guide, which shows how we do our lay-outs. Our lay-outs are used for all the characterizations of the MGTs for eeach and every standard (there are some 40+ of these), so these lay-outs have been refined with each new generation to the point where we seem to know what works, and what doesn't work.

Unless you have extensive field and wave modeling software and fields and waves experience, I do not suggest doing something different.

We generally assume that we are on a pcb where there are no 'other' circulating currents (there is no large current loop from something on one side of the device, to something on the other side of the device).

All circulating currents we assume are there, are from our own IO pins (driving things like DDR SDRAMs, etc.).

Austin

Why did you do that? It's almost certainly a very bad move indeed. You should have one ground plane. You can separate power planes in to mini-planes, that's fine. Connect power planes together with ferrites, that's fine also. However, the ground plane should stay as one plane. HTH., Syms.

Actually, I will split several ground planes for several parts of the whol circuit. Among that, I plan to give a isolated planelet to FPGA PLL (Cyclone II ep2c35). Of course, I know the advantage of a integral gnd plane,but in a rea design that is not easy to achieve. In a mixed signal design, if you kee the single gnd plane integral, that will be a disaster for the analo circuit.

Leon('commone' :))

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Hi Commone, Let's just make sure we're talking about the same thing. The ground plane is the one that attaches to all the GND pins, right? Zero volts, 0V.

You are wrong* to split this plane(s). I agree that you can, and maybe should, split the power planes, the ones that carry the supply voltages, i.e. 3.3V, 1.2V etc. However, if you split the ground planes you are in a world of pain when signals cross from one plane to the next. Their reference changes and the return current path has to go through one of your ferrites.

Let me put it this way. If you design with one ground plane for all the circuit, exactly what is the mechanism for noise coupling from one area to another through this plane? Assume that the power supplies for each section are suitably isolated.

Finally, why don't you go and look at some mixed signal IC manufacturers and have a look at their demo boards. They don't split ground planes. You will find some old app notes that claim split planes are good, but the boards they make don't have these splits.

HTH., Syms.

*There are very rare cases where the ground plane needs to be split, usually involving isolation requirements. When this happens it's very difficult to design properly.

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ferrites.

I will keep the digital signals not overlap the analog plane and th analog signals not overlap the digital plane. Will the digital retur current go into analog plane and where is the volt drop across the FB? If you do want to mix the digital and analog traces in the same area noone can do anything to save the analog circuits.

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I agree, you need to keep analog components away from fast switching digital ones. However, there's no need to cut the ground plane up to achieve this. It makes it complicated, and much more likely to go wrong.

Right, I see this a lot. They say "It may also be beneficial to use separate ground planes for the analog and the digital circuitry.", but then singularly fail to say what these benefits are. The reason they don't explain this is because there are almost no benefits, only drawbacks. I ask you again, presuming you physically separate the digital and analog circuits and power supplies, how does noise couple over a single shared ground plane?

HTH., Syms.

I'm wondering if the right thing to do is to let you "fail" which is why I haven't interjected. I've read many A/D data sheets that talk about splitting the grounds for a common point connection. I did a board about a decade ago with some pretty reasonable mixed signal portions in the path. To keep my VCO clean or to make my post-D/A 5-pole filter clean before hitting a quadrature modulator, I had my ground and power "cleanly" split but with hard copper at one point in the region, not a ferrite. When I passed single ended signals, I ran them over this small connection between ground regions. I also used differential signals where I figured crossing the ground split would be acceptable.

When all was done, my EMI was lousy. The ground on the BNC connector had a good 2 mV or so of signal different from the ground on the receive side in the same chassis. The BNC cable that connected the TX to the RX turned into one big loop antenna. It took too many aborted attempts to find the root of the problem before I had isolated drivers milled into a block of brass to get the problem licked. With power AND ground filtered in this $75 piece of hardware fed by a differential signal, I was finally able to get rid of the singal on my ground plane. I'm convinced (partly because of radiative probing of the board) that the root cause of the EMI was my ground splits.

You can filter the power and make many little power islands. If you try to make too many ground islands, ESPECIALLY through ferrites rather than the "single point connection" of hard copper, your board will become quite the little AM station.

I wish there was more hard evidence available to engineers doing early designs in their career about how to properly design a grounding system for low noise analog. I didn't find any and I paid at least 2 months in our tiny EMI prescan chamber. There's a small dent in the metal wall that roughly matches the contour of my forehead. I don't recommend splitting the ground planes.

- John_H

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Symon: Ideally,if we physically separate the digital and analog circuits and power supplies,noise will not couple over a single shared groun plane. But the noisy digital cicuits will make the ground plan nosiy.Right? Is it equivalent to apply a vlot drop in the single gn plane? Will the analog circuit be influenced? But when we split the gn plane, and connect them with ferrite beads or schottky diodes. That wil supply a great impendence for some high frequency noise that want to g into the analog gnd plane(Pls do not doubt the existence of these nois cause the digital gnd plane maybe damaged by handreds of vias and other holes ). And these nosie will pick other paths with relatively lo impedence in the digital gnd plane to return its source. So for the nois sensitive analog circuits, we do have a strong reason to give them seperated gnd plane. In some high speed AD data capture card, plp tend t seperate the gnd plane into analog gnd plane and digital gnd plane.

Leon,

Wrong. The ground plane is your reference. Again, what is the mechanism you fear will couple noise into your analog circuitry.

Why would high speed current want to travel from the digital section to the analog section? You're not going to route digital signals through the analog section, so I don't see what you mean. And, how do a few via holes make any difference? A copper plane has exceptionally low impedance. If you earthed a 'scope probe at one point on the ground plane, you won't see any noise as you move the probe around the plane. Unless, of course, you cut a great big slot in it.

Not if they know what they're doing, they don't.

OK, you've made up your mind, you go for it. But, make sure you come back and read this thread in 8 months time while your board is failing the CE mark for emissions. I hope you'll learn for the next time. Also, rather than take advice from me on the FPGA newsgroup, why not ask your question on a more appropriate forum, like the SI-LIST mailing list. Maybe they can help you where I have failed.

Good luck, Syms.

John_H You mean that the best thing to do is to keep a integral gnd plane and a the same time do not overlap the digital and analog regions on differen signal layers?

The integral ground plane is your best bet for EMI performance. My own concern when I split up my ground planes in my unintentional radiator was to keep the digital current surges from affecting the low impedance (though more than a 0-pH per square impedance) ground plane when they passed

*through* an analog section. Perhaps this same goal can be achieved through simple positioning of the analog circuitry.

The digital and analog signals can share the same signal layer. Crosstalk between regions goes out to several times the spacing from the signals to the reference plane, but that's not very far. It may be the better way to "isolate" the analog and digital realms is to ferrite-couple the power into tiny islands used by the parts with fully adequate local bypassing but avoid using those power planes as a reference. If you hammer the GND and VCC planes with your digital logic and use the same supply for the analog section, somethings' gotta give when the current surges. If your VCC planes are isolated through the ferrites, hammering on the FPGA power plane will be hard to "hear" in the filtered analog power plane.

Keeping the ground reference will help to avoid generating ground differentials in any ground sections that are effectively tied together in a loop. Having one hard ground (often consisting of 2 or more physical ground planes with many vias, particularly where signals switch between reference planes) will keep the signals happy by maintaining a common return path and keep the design happy by not *forcing* the current surges to push the ground plane around. The common power and ground planes *will* force the ground plane to wiggle with those current surges when the voltage drops since all the bypassing caps keep things very symmetric.

Reread Symon's posts. I doubt you'll find any hard evidence out there countering his comments (the ADI data sheets are more anecdotal, not hard evidence that splitting planes benefits anything at all).

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Symon: I am appreciate for your advice. You make me clarify some concepts. Mayb I am deeply misleaded by some people's design, you know I do not hav enough experience in the field. I think I will take your advice. Thank yo and John_H again. Leon,

Hi Leon, Cool! I'm sorry if I was a little brusque in my last post; I'm not having a good day with my simulator, I shouldn't take it out on you! Best regards, Syms.

Check this out

This guys agrees with me! Wooo! Warning:- Other people may have different opinions!

Cheers, Syms.

The only way other circuits can make the ground plane noisy is by passing large currents across it. Proper layout of noise generating sections to contain all return currents will keep these current flows contained to areas away from the sensitive circuits. In some cases it can be necessary to place shields over noise generators, or even over sensitive circuits, to improve isolation, and to enclose the currents.

Jon

If you have mixed-signal devices--ADCs, DACs--with, say, digital control signals, then a split plane is a real problem if those signals have to cross the split.

-a

I think there are 2 cases where the voltage developed between 2 points of a solid gnd plane can be big enough to be a problem:

1. There are huge currents in the system such as when there are electric motors involved;
2. The analog circuit has high input impedance and very sensitive such as the case with pro audio for example.

I myself routinely design mixed RF/digital boards and for this purpose I chose to use a single ground plane long ago, however I am not convinced this approach will work well for the 2 cases mentioned above.

/Mikhail

Interesting article. That one definitely goes into the data bank fo future reference. Thanks.

Symon,John_H : Thank you for your help, I still have several questions to ask you.

1)If two signal layers share the same reference gnd plane, will thei return currents react each other?

2) I see a ten-layer stack recommended by ?High-speed digital design (Johnson) P220 From top to bottom:

------------------------- signal(horizontal routing) signal(vertical routing) gnd signal (horizontal routing) signal(vertical routing) signal (vertical routing) signal( horizontal routing) power signal (horizontal routing) signal(vertical routing)

------------------------- I don?t think it is good especially for a mixed-signal board. For example it uses a power plane as a reference, at the same time if I split it int several mini-planes, that will cause EMI, right?

3)I plan to make my board as a six-layer one, what is best layer-stack yo think? (In my board, there are 3 volt levels: 3.3V fo FPGA,ADV7181,ADV7123;1.8V for ADV7181; 1.2V for FPGA ) Could [Top--gnd(integral :))--signal--power--gnd(integral :))--bottom] b the best?