ng more than 10 states must have a clock gating function to save power cons umption:
d not be generated to keep the state unchanged and save power consumption.
the fact that the state does not change. A flip flop that is clocked but d oes not happen to change its output does not consume much power. The power is needed to charge/discharge the loads that are being driven. Any decrea sed power consumption would have to do with the decrease in power in genera ting the clock input to the flip flop. But shifting from a common clock to adding a gate that generates a clock probably does not lower power since t he same number of clock signals are being generated. If the gated clock ro uting is a higher capacitive route then when using a free-running clock the n you can consume more power. This is the result when trying to implement gated clocks in FPGA. ASIC will be different.
ion may not be necessary because too few state machines are implemented in any normal application.
escribe in an FPGA results in an increase in power consumption. I provided you with all of the details for your sample design. The results of that a nalysis are not "because too few state machines are implemented", it is bec ause gated clocks in FPGA use more power, not less. Again, that was with y our sample design of that time which appears to be the same thing you are r eusing here.
VHDL as follows after the post is posted:
e apparent usage of a possibly free running clock.
ays it is. No worries though, synthesis tools should optimize out the 'els if' and leave the assignment 'WState > > elsif WState /= WState_NS then -- WState /= WState_NS is n ecessary!
nd claiming since the code is not complete and does not compile...as usual.
do not find Hans of
r earlier publication. The publication will happen about 14 weeks later sin ce its filing date.
to IEEE Transaction of circuits and System for publication. The review proc ess may take up to 3 months.
cannot disclose any details about my invention until the transaction agree s to publish my paper 3 months later or rejects my paper in 1 or 2 weeks.
s almost the same as conventional method would generate, or maybe even simp ler than conventional method.
I think you missed the mark by a wide margin on this one. The logic needed for the clock gating is this...
elsif WState /= WState_NS then
This is not so trivial compared to the FSM itself, especially in an ASIC. I would estimate it is approximately the same amount of logic in general.
in state machines for the Cache II control. If they don't care about the p ower saving or they have implemented some scheme in the implementation, my invention would be of few values, or otherwise it would be worth million of dollars.
For a patent to be valid it has to be non-obvious to a practitioner in the field. I don't know how this is non-obvious to someone in the field of CPU design. You may obtain a patent, but then lose a patent defense case in c ourt. But again, I didn't think cell phones would take off and now I have two.
out how to implement a state machine with clock gating function.
What exactly is your "invention"??? Clock gating is nothing new. It is ap plied to many parts of a CPU. Is your invention the idea of applying it to the individual FSMs in a CPU cache? So if someone instead applies it to g roupings of FSMs in a CPU cache they will have worked around your patent.
gister and sell the application at
-to-ast/. I know the website because Google refers to the website and indic ates they are a member of the site. I expect that Intel, IBM, AMD, Apple ma y also be the members of the website. The site asks for the selling price d uring registration. So it is important for me to assess my invention's valu e properly.
What value have you assessed so far?
is website, not mention taking part in the discussion of my post.
ore my registrations in the patent selling website.
input for 8 registers in the block. Altera may be in the same situation. So clock enable is never a new thing and we don't have to pay attention to ho w the clock trees work. For a CPU design, in my opinion, logic design and c lock tree design are 2 separated domains one after another, and logic desig ners never have to pay attention to the clock trees.
Clock enable and clock gating are not the same thing. Clock enable saves p ower by not changing the FF state, but if the FF input is the same as the o utput the state won't change anyway.
Here is something to consider. Clock gating saves power compared to clock enabling by reducing the power consumed in the clock tree. How much of the clock tree will you actually be gating with a fine grained approach? Cloc k trees are exponential structures with a multiplier for the fan out at eac h level. With this fine grain approach you are only saving power in the fi nal level and in fact, may be adding a level if your clock gating control i s at a finer resolution than the last level of clock drive.
Generally clock gating is used at a high level to gate the clock to section s of a chip. I expect it is seldom if ever used at a low level because the power saved is not optimal and the logic required is maximal.
Rick C.
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