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Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Tuesday, January 8, 2019 at 12:26:39 PM UTC-8, gtwrek wrote:
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w do you handle it using your scheme?
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Hi Mark,

You really has good memory!!!  

I posted a post with title: "What is largest number of state machines in a  
chip" at this FPGA group several years ago.

Here are tons of state machine patents about how to design a L2 cache. I li
st only the search word "L2 cache inassignee:intel" and you can find throug
h Google there are 4,830 patents filed and issued by Intel, the search word
 "L2 cache state machine inassignee:intel" and it leads to 4,360, each of t
hem is related to a type of state machines.  

I believe that anyone cannot be accounted as a professional digital circuit
 designer if he does not seriously consider or design a state machine.  

One of my hobbies is to look at patents filed by Intel, IBM, AMD, Xilinx an
d Altera. Reading Xilinx and Altera' patents gives me the knowledge on how  
they design their FPGA chips. Reading Intel, IBM and AMD' patents gives me  
the knowledge on how they design something very complex and new technology  
trend. And through the reading I find many topics for me to further develop
.  

I disagree with your following opinion:
"I've not designed a CPU cache.  But I can pretty much guarantee that  
whomever designed that CPU cache you're thinking about did NOT model  
the design as such (a lot of state machines running in parallel).  To  
be frank, I can see the entire design being done without implementing  
a "state machine" at all. "

Here is an Intel patent: US8493397B1: "Circuit for placing a cache memory i
nto low power mode in response to special bus cycles executed on the bus"

https://patents.google.com/patent/US8493397?oq=L2+cache+state+machine

https://patents.google.com/patent/US20140156931?oq=L2+cache+state+machine

I agree with your following opinion:
"a lot of state machines running in parallel".

After my invention all state machine design will be benefited to be in lowe
r power status, no matter what type of state machines is, and the logic res
ource usage is less than a conventional synthesizer would generate.  

Rick,
I disagree with your opinion:
"elsif WState /= WState_NS then  

This is not so trivial compared to the FSM itself, especially in an ASIC.  
I would estimate it is approximately the same amount of logic in general. "

In my invention there is no one single logic gate generated for comparison  
"WState /= WState_NS". Is it obvious to you?  

That is the best point of my invention.

Thank you.

Weng



Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
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Proof by counter-example.  My coworked is an excellent "professional
digital circuit designer" and has been for over 30 years.  He does use a
"state machine" to model any of his designs.  He doesn't like the model.
Again, we're talking about using a model as a tool.  That model doesn't
work for him.  He has others that work quite nicely.

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That's a non-sequiter: There's nothing in that patent search that says
the designer is using a state machine model to design the CPU cache.  
That's all part of your imagination.  

A "digital circuit" is just FF's and combinatorial gates tied together
in clever ways.  Whether you apply a "state machine" model to the circuit  
is just something between your ears.  Most of the tools see just FF's,
gates (or LUTs), and timing paths.  

I assert (without eny evidence whatsoever) that whomever designed that CPU
cache memory at Intel did NOT model it (in his head or otherwise) as
100,000 or more state machines running in parallel.  That's just crazy.

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You're still not hearing me.  If you have some Super Snazy Algorithm
that does some magic low power thing targetting state machines, then the
Super Snazy Algorithm would also be capable of targetting ANY digital
circuit.  (If I recall, most FPGA Low power optimizers run rather late
in the implementation process - i.e. after synthesis and "state machine"
optimizations)  

As a skeptical engineer (any engineer that's been around for any time
whatsover fits this description) I have sincere doubts in your Super Snazy
Algorithm.  Bright folks have been designing low-power tools for quite
some time.  I've doubt there's any room for improvement (at least in
the digital logic sense).  And digitally, the problem's not hard to
define at all.  The devil is in all the details with respect to timing,
and other optimization metrics.  (Hint if your only metric is "logic
resource usage" then you're not understanding the full problem by a long
shot).

On the other hand maybe you're a digital logic savant, and are seeing
new and creative solutions.

Good luck with your further patent googling, and applications.  

Regards,

Mark  



Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
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                                                                    ^^^
---- Arg! Edit to make my point -------------------------------------

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Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Mark,

"I assert (without eny evidence whatsoever) that whomever designed that CPU  
cache memory at Intel did NOT model it (in his head or otherwise) as  
100,000 or more state machines running in parallel.  That's just crazy. "

Here are the facts, you are welcome and no matter whether you agree or not:
1. 6M L2 cache, the largest L2 cache I can search for with a commercial CPU;  

2. Every 64 bytes in L2 cache constitute a cache line;

3. Each L2 cache line works independently;

4. Each L2 cache line has at least one state machine to control its data or instructions in coherence. I will not be surprised that each L2 cache line may have up to 8 state machines to control its working.  

4. Each L2 cache line has at least one state machine to control its data or instructions in coherence. I will not be surprised that each L2 cache line may have up to 8 state machines to control its working.

4. Each L2 cache line has at least one state machine to control its data or instructions in coherence. I will not be surprised that each L2 cache line may have up to 8 state machines to control its working.

4. Each L2 cache line has at least one state machine to control its data or instructions in coherence. I will not be surprised that each L2 cache line may have up to 8 state machines to control its working.

4. Each L2 cache line has at least one state machine to control its data or instructions in coherence. I will not be surprised that each L2 cache line may have up to 8 state machines to control its working.


1. IBM: Cache-coherency protocol with upstream undefined state
https://patents.google.com/patent/US6374330

2. IBM: Cache-coherency protocol with recently read state for data and instructions
https://patents.google.com/patent/US5996049

3. NVidia: State machine control for a pipelined L2 cache to implement memory transfers for a video processor. https://patents.google.com/patent/US8493397

Thank you.

Weng

  

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
So much wrong.

Any marginally competent cache designer understands that only one cache lin
e is accessed at a time. So the cache is designed as a RAM with data, tags,
 and state. Each cycle the data, tags and state are read, and a single stat
e machine is used to generate the next state, which is written back into th
e RAM.

There are plenty of papers on flip flop design that detects whether the new
 data is different from the present state, and uses that to generate a cloc
k pulse only if necessary.  

On Tuesday, January 8, 2019 at 6:12:43 PM UTC-5, Weng Tianxiang wrote:
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PU  
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t:
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PU;  
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or instructions in coherence. I will not be surprised that each L2 cache li
ne may have up to 8 state machines to control its working.  
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or instructions in coherence. I will not be surprised that each L2 cache li
ne may have up to 8 state machines to control its working.
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or instructions in coherence. I will not be surprised that each L2 cache li
ne may have up to 8 state machines to control its working.
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or instructions in coherence. I will not be surprised that each L2 cache li
ne may have up to 8 state machines to control its working.
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or instructions in coherence. I will not be surprised that each L2 cache li
ne may have up to 8 state machines to control its working.
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structions
mory transfers for a video processor. https://patents.google.com/patent/US8
493397
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Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Thursday, January 10, 2019 at 2:02:22 PM UTC-8, snipped-for-privacy@gmail.com wrote:
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ine is accessed at a time. So the cache is designed as a RAM with data, tag
s, and state. Each cycle the data, tags and state are read, and a single st
ate machine is used to generate the next state, which is written back into  
the RAM.
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ew data is different from the present state, and uses that to generate a cl
ock pulse only if necessary.  

Congratulation!

Your post is the best and most valuable post in this thread!

Invincible! Marvelous! Smartest!

Your post makes me shameful and speechless!

Hope you join my later post.

I will continue to pursue my next sets of inventions!

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Thursday, January 10, 2019 at 10:52:13 PM UTC-5, Weng Tianxiang wrote:
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e:
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 line is accessed at a time. So the cache is designed as a RAM with data, t
ags, and state. Each cycle the data, tags and state are read, and a single  
state machine is used to generate the next state, which is written back int
o the RAM.
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 new data is different from the present state, and uses that to generate a  
clock pulse only if necessary.  
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LOL!  So can you share your secret comparison using no gates?  

  Rick C.

  --- Get 6 months of free supercharging
  --- Tesla referral code - https://ts.la/richard11209

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
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If this is from the state machine code you posted on Jan 5, I already point
ed out that the "WState /= WState_NS" is not necessary in that design eve
n though your code comment said it was needed. Logic synthesis will optimiz
e it out.  In can do that because your posted design is not an example of a
 gated clock design.  

However, if you move "WState /= WState_NS" to create logic that is used t
o generate a gated clock in some fashion that is used to clock the state ma
chine, then there will be extra logic generated to implement "WState /= W
State_NS" which will consume power.

So what are you talking about...
1. Your earlier posted code that is not of a gated clock design?
2. Some other unpublished gated clock design where you are making unsubstan
tiated claims?

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Well that's too bad.

Kevin

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Kevin,

In my invention, all state machines will be synthesized to have clock gating function, no matter whether or not it is coded to have clock gating device!

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
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ing function, no matter whether or not it is coded to have clock gating dev


Then anything using your invention...
-Will use additional logic.  The power consumed by that logic will have to  
be subtracted out from whatever power savings might get realized from clock
ing less frequently.  
-Will be impossible to get timing closure in an FPGA environment, maybe ASI
C tools can handle it.
-Will consume more power in an FPGA, TBD if it will in an ASIC.
-Will not end up saving much power since state machine consume a relatively
 small portion of the power... the majority of the power is consumed by the
 data path that is being controlled.

So, function, performance, and power are all negatively impacted.  Is anyon
e here interested?

You also didn't answer my question about if you were referring to your Jan  
5 code or some unpublished code...same 'ol story with your ideas.  

Kevin Jennings

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
By the way, the whole idea of not clocking a flip flop except when needed t
o change state is loooooong ago pre-existing knowledge.  The storage device
 is called a toggle flip flop, the ripple counter being the classic example
 of a function that is easy to understand and uses the device...you did inc
lude that in your description of prior art in your patent disclosure, right
?

Kevin Jennings

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Kevin,

1. No source code is provided for a testing bench except demonstrating my ideas.

Then anything using your invention...  
2. "-Will use additional logic."
No additional logic is used except a clock gating device.

3. "  The power consumed by that logic will have to be subtracted out from whatever power savings might get realized from clocking less frequently. "
No additional power is consumed on no additional logic.

4. "-Will be impossible to get timing closure in an FPGA environment"
Wrong! Xilinx has a built-in clock enable input for 8 register in a LUT6 block.

5. "-Will consume more power in an FPGA."
Wrong!

6. "TBD if it will in an ASIC." I don't know what "TBD" stands for.

7. "-Will not end up saving much power since state machine consume a relatively small portion of the power"
It is right if for a single state machine, but not correct when dealing with 100,000 state machines.

8. I just mentioned that skipping a cycle pulse would save power. No more than that is mentioned. It is not my business.

Thank you.

Weng


Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Tuesday, January 8, 2019 at 8:04:01 PM UTC-5, Weng Tianxiang wrote:
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 ideas.

You stated in an earlier post "In my invention there is no one single logic
 gate generated for comparison "WState /= WState_NS". Is it obvious to yo
u?" but the code being referenced was not from a gated clock design so ther
e is nothing 'demonstrating your idea' whatever that may be.
  
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Did you not even notice your use of the word 'except' after you typed it?

No matter.  So this 'clock gating device', either has only one input (which
 is the only thing that would not require logic resource to implement) or i
t has more than one input and can generate the correct gated clock output w
ithout any logic resources, which means it works by magic.  The absurdity m
eter is pegged at the highest setting with this claim of yours.

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m whatever power savings might get realized from clocking less frequently.  
"
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Well of course.  Why would the 'operates by magic' clock gating device whic
h is only needed with your "invention" require any power in order to operat
e?  Absurdity meter has gone off scale.

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block.
You've been told this before by others, but a clock enable input is not the
 same thing as a gated clock.  Specifically, in typical electrical engineer
ing parlance, a 'clock enable' signal modifies the data input to a flip flo
p, not the clock input.  'Clock enable' signals do not modify the clock in  
any way.  Do some more research, this is a pretty basic logic design concep
t.

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I am correct and I sent you the full details back in 2010.  The governing N
DA for that work is no longer in force but I won't post all the details her
e that back my claim in order to avoid embarrassing you any further.  If yo
u would like to post your actual design, methods and measurements here to p
rovide evidence to justify your stance, feel free.  Simply making statement
s and claims is not evidence.

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You seem to have a lot of outages of Google at your place.

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tively small portion of the power"
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ith 100,000 state machines.
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No, the number of state machines does not matter since they will (or should
) be controlling much larger stuff that would consume the bulk of the power
.  If you have 100,000 state machines controlling 10,000 things in a data p
ath, you likely have incompetently designed state machines.

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 than that is mentioned. It is not my business.
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Yes, you stated that but can provide no evidence to back that claim.  Witho
ut that, you're just making unfounded statements, many of which are clearly
 incorrect and have been pointed out to you...for many years now.

Kevin Jennings

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Kevin,

I thank you for your help many years ago.

It is not correct:  
"a 'clock enable' signal modifies the data input to a flip flop, not the clock input.  'Clock enable' signals do not modify the clock in any way."

When a CLOCK ENABLE is deasserted, no clock pulse will feed a FF, and the FF will keep unchanged on the next cycle. If a CLOCK ENABLE is asserted, a clock pulse will feed a FF, and the FF will be updated on the next cycle.    

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Richard and Kevin,

Here is a copy from Wikipedia "clock gating":
https://en.wikipedia.org/wiki/Clock_gating

Clock gating is a popular technique used in many synchronous circuits for r
educing dynamic power dissipation. Clock gating saves power by adding more  
logic to a circuit to prune the clock tree. Pruning the clock disables port
ions of the circuitry so that the flip-flops in them do not have to switch  
states. Switching states consumes power. When not being switched, the switc
hing power consumption goes to zero, and only leakage currents are incurred
.[1]

Clock gating works by taking the enable conditions attached to registers, a
nd uses them to gate the clocks. A design must contain these enable conditi
ons in order to use and benefit from clock gating. This clock gating proces
s can also save significant die area as well as power, since it removes lar
ge numbers of muxes and replaces them with clock gating logic. This clock g
ating logic is generally in the form of "integrated clock gating" (ICG) cel
ls. However, the clock gating logic will change the clock tree structure, s
ince the clock gating logic will sit in the clock tree.

Clock gating logic can be added into a design in a variety of ways:

Coded into the register transfer level (RTL) code as enable conditions that
 can be automatically translated into clock gating logic by synthesis tools
 (fine grain clock gating).

Inserted into the design manually by the RTL designers (typically as module
 level clock gating) by instantiating library specific integrated clock gat
ing (ICG) cells to gate the clocks of specific modules or registers.
Semi-automatically inserted into the RTL by automated clock gating tools. T
hese tools either insert ICG cells into the RTL, or add enable conditions i
nto the RTL code. These typically also offer sequential clock gating optimi
sations.

Any RTL modifications to improve clock gating will result in functional cha
nges to the design (since the registers will now hold different values) whi
ch need to be verified.

Sequential clock gating is the process of extracting/propagating the enable
 conditions to the upstream/downstream sequential elements, so that additio
nal registers can be clock gated.

Although asynchronous circuits by definition do not have a "clock", the ter
m perfect clock gating is used to illustrate how various clock gating techn
iques are simply approximations of the data-dependent behavior exhibited by
 asynchronous circuitry. As the granularity on which you gate the clock of  
a synchronous circuit approaches zero, the power consumption of that circui
t approaches that of an asynchronous circuit: the circuit only generates lo
gic transitions when it is actively computing.[2]

Chip intended to run on batteries or with very low power such as those used
 in the mobile phones, wearable devices, etc. would implement several forms
 of clock gating together. At one end is the manual gating of clocks by sof
tware, where a driver enables or disables the various clocks used by a give
n idle controller. On the other end is automatic clock gating, where the ha
rdware can be told to detect whether there's any work to do, and turn off a
 given clock if it is not needed. These forms interact with each other and  
may be part of the same enable tree. For example, an internal bridge or bus
 might use automatic gating so that it is gated off until the CPU or a DMA  
engine needs to use it, while several of the peripherals on that bus might  
be permanently gated off if they are unused on that board.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Tue, 8 Jan 2019 21:10:58 -0800 (PST)

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I heard long ago that the 'clock enable' signal in Xilinx
FPGAs does not affect the clock signal. This is likely to allow
sharing clock edge detection, and to minimise the routing to a
block of flops with shared clock signal. Patent here [1].
  
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This is from a logic user's guide, with simplified explanation
based on the implementation of a single flip-flop, and is not
intended to be a circuit description.

Suggestion: 'The hardest thing to know is (the extent of) what
we do not know.'  

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Jan Coombs
--

[1] Clock enable control circuit for flip flops  
United States Patent 6466049 [2002]
We've slightly trimmed the long signature. Click to see the full one.
Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
snipped-for-privacy@murmic.plus.com says...
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Xilinx recommends clock gating be fed through bufgce to prevent skew  
and timing issues (you also gain good fanout of course) if feeding large
enough numbers of blocks.,
Vivado automatcaly moves the gating to the enable path for flip flops
or latches (can be manually overriden though I've not done that yet)  

As for writing patents based on other peoples patents - this thread confirms
the obvious:

To quote Daniel Whitehall:
 "Discovery requires experimentation"
                    Marvels agents of SHIELD  

john

=========================
http://johntech.co.uk
=========================

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi,  
Thank you for more people involved in this discussion.

1. Here is my prior art description of FIG. 1 on how a clock gating device  
is used. Clock gating device is used in my invention as a prior art device.
  

[0009]        FIG. 1 is an interface diagram for any type of clock gating devi
ce currently known in the art. These types of clock gating devices have the
ir clock input ?>? coupled to a state machine?s clo
ck source, with its clock pulse output C driving a clock pulse on the next  
cycle if the clock enable input E is asserted on the current cycle.

2. Because of the strict requirement of IEEE Transaction requirement on pap
er's originality, I cannot disclose any details of my invention until about
 3 months later. The paper contains 11 double column pages, excluding the a
uthor's biography, and 10 related schematic diagrams of related state machi
ne's circuits.

From the schematic diagrams you can immediately know that the full circuit  
of a state machine is much simpler than any counterpart of a conventional s
tate machine circuit with clock enable logic naturally generated without an
y extra logic.

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Wednesday, January 9, 2019 at 11:44:56 AM UTC-5, Weng Tianxiang wrote:
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t of a state machine is much simpler than any counterpart of a conventional
 state machine circuit with clock enable logic naturally generated without  
any extra logic.
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The schematic of a ripple counter implemented with T flip flops is also qui
te simple when compared to that of a conventional synchronous counter.  As  
I previously posted, use of T flip flops rather than D flip flops (and the  
consequential generation of gated clocks to support synthesis using T flip  
flops) is existing prior art that is covered in old textbooks.  Your chosen
 subset of use cases such as state machines is a restriction over what is a
lready out as prior art which covered all synchronous machines.

Kevin Jennings

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
  ?Your chosen subset of use cases such as state machines is a rest
riction over what is already out as prior art which covered all synchronous
 machines. ?

My method only applies to a state machine circuit and defines many brand ne
w concepts for a state machine.

The method is useless for FPGA as nobody cares about a low power state mach
ine circuit. The saver of my invention is the case of CPU' 100,000 state ma
chines for 6M L2 cache.  

Weng

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