Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

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Hi,

Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine.

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 05/01/2019 05:29, Weng Tianxiang wrote:
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Clock gating can be written in any language you like. It's FPGAs that  
don't support clock gating.

Nicolas

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Saturday, January 5, 2019 at 3:44:39 AM UTC-8, Nicolas Matringe wrote:
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gating function?
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erilog has the clock gating function for a state machine.
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Hi Nicolas,

I am asking if Verilog or SystemVerilog has the ability to automatically ge
nerate a state machine with clock gating function without any extra new sta
tements? For example, do they have an attribute if the attribute being set  
the state machine generated will have the clock gating function?

At least VHDL-2008 does not have the ability.

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 05/01/2019 15:18, Weng Tianxiang wrote:

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Well then I don't know what that "clock gating function" is, I'm sorry.

Nicolas

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

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What do you mean 'extra new statements'?  This looks to me like clock
gating:


input clk;
input enable;
wire gated;

assign gated = clk & enable;

always @(posedge gated) begin
...
end


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I don't know what you mean by that.  (System)Verilog's abstraction doesn't
generate abstract state machines, it just allows you to write them.  
Whatever synthesis tools do with that code is up to them.  I presume tools
could pick up the above style if they so desire (I don't know if any ASIC
tools do but expect they would).

Theo

Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Apparently you cannot, but yes it can be done by others. It can also be written in VHDL but apparently you don't like how to do that so you state that it can't be done.  Perhaps you should more clearly state your problem.  

Kevin

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/4/19 11:29 PM, Weng Tianxiang wrote:
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One big question is what do you mean by 'clock gating'

As was mentioned, one option for this is to do something like

assign gatedclk = clk & gate;

or sometimes

assign gatedclk = clk | gate;

and then us the gatedclk as the clock. The big issue with this is that
you need to worry about clock skew when you do this, as well as glitches
(the second version works better for gate changing on the rising edge of
clk, but needs to be stable before the falling edge.)

A second thing called 'clock gating' is to condition the transition on
the gate signal, something like

always @(posedge clk) begin
  if(gate) begin
... state machine here.
  end
end

This make the machine run on the original clock, but it will only change
on the cycles where the gate signal is true.

VHDL can do the same.

There is no need for a 'special statement', you just do it.  If doing
the first version, of actually gating the clock, you may want to use
some implementation defined macro function to buffer the clock and put
it into a low skew distribution network, like may have been done for the
original clock.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Saturday, January 5, 2019 at 2:35:28 PM UTC-8, Richard Damon wrote:
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Hi Theo and Richard,

Thank you for your help.

Using clock gating function is to save power consumption. Why I ask the question is:

A cache line in Cache I, Cache II or even Cache III in a CPU usually has 64 (2**6) bytes and each cache line must have a state machine to keep data coherence among data over all situations.  

For a 6M (2**22 + 2**21) bytes cache II (the most I have seen in current market) a CPU must have at least (2**16 + 2**15) state machines, ~= 100,000, and those ~100,000 state machines don't change states most of time.

In above situation each of the ~100,000 state machines with each having more than 10 states must have a clock gating function to save power consumption:  

when it will not change states on the next cycle, a clock pulse should not be generated to keep the state unchanged and save power consumption.

Do you think if it is reasonable?

For an application implemented in a FPGA chip, the clock gating function may not be necessary because too few state machines are implemented in any normal application.

Actually I realized how to implement the power consumption scheme in VHDL as follows after the post is posted:

type STATE_TYPE is (s0, s1, ..., Sn);

signal WState, WState_NS: STATE_TYPE;

...;
a: process(clk)
begin
   if rising_edge(clk) then
      if SINI then
         WState <= S0;

      elsif WState /= WState_NS then --  WState /= WState_NS is necessary!
         WState <= WState_NS;
      end if;
   end if;
end process;

b: process(all)
begin
   case WState is
      when S0 =>
         if C00 then
            WState_NS <= S1;

         elsif C01 then
            WState_NS <= S2;

         else
            WState_NS <= S0;
         end if;

      ...;
   end case;
end process;

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/5/19 8:23 PM, Weng Tianxiang wrote:
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One issue with gated clocks is that each gating of the clock needs to be
considered a different clock domain from every other gating of the clock
and from the ungated clock, because the gating (and rebuffering) of the
clock introduces a delay in the clock, so you need to take precautions
when the signal passes from one domain to another. A FPGA might have,
and a gate array may provide a special circuit to generate a set of
gated clocks that will be kept in good enough alignment to not need
this, but then that would be a special application macro that needs to
be instanced.

Second, the power consumption between my first and second method (actual
gating of the clock and using a clock enable) is primarily in the power
to drive the clock line as the clock enable also keeps the state the
same in the 'skipped' clock cycle.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Saturday, January 5, 2019 at 6:28:35 PM UTC-8, Richard Damon wrote:
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Hi Richard,

There are 2 things to consider on how to generate a clock gating function:
1. Generate CE logic.
2. Make gated clock signal working properly.

You address the part 2) and I emphasize on the part 1).  

Is it complex to generate CE logic?

In my understanding generating a clock pulse is consuming more power than skipping the clock pulse.

I want to know if each of CPU ~100,000 state machine implementation actually has clock gating function.  

Based on your code I think it is reasonable to think each of CPU ~100,000 state machine implementation actually has clock gating function.

Only CPU designers know their implementation. I need the information.

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/6/19 12:08 PM, Weng Tianxiang wrote:
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Actually gating the clock is a single gate (but then in an ASIC it can't
drive much logic, so things start to get more complicated). Making it
work gets things much more complicated, and probably gets you out of the
domain of portable Verilog or VHDL. That is the nature of clock trees.

Thus, step one is in a sense trivial if you are ignoring step two, but
doing step one while ignoring step two is worthless.

I personally don't know whether it is simpler/better to add the clock
enable functionality to the flip flops or gate the clock and deal with
all the timing/buffering issues, and it wouldn't surprise me if it
turned out that which is better very much depends on the process and
other criteria.

The only real answer would be to talk to the process people, but my
guess is that the answer is very much proprietary, and unless it looks
like you are willing and planning on spending the big bucks to actually
do this, won't waste their time talking about it.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Sunday, January 6, 2019 at 1:20:16 PM UTC-5, Richard Damon wrote:
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ock gating function?
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temVerilog has the clock gating function for a state machine.
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has 64 (2**6) bytes and each cache line must have a state machine to keep d
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ent market) a CPU must have at least (2**16 + 2**15) state machines, ~= 1
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ng more than 10 states must have a clock gating function to save power cons
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00 state machine implementation actually has clock gating function.
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Sure, in full custom ASICs it is not uncommon to gate the clock.  In fast c
hips the clock tree design can consume half the dynamic power in the chip.  
 So gating the clock can bring significant power savings.  However, the clo
ck gating being described here is over far too small a portion of the chip  
to be effective on many levels if I understand what is going on.  The OP is
 talking about 100,000 identical state machines, one for each cache item.  
I believe what he is talking about as FSMs are really just a handful of FFs
 but I'm not sure.  If so, the clock gating logic is nearly as large and so
 would consume nearly as much power and area as the logic it is controlling
.  

Will it be practical to design 100,000 clock gating circuits to control 100
,000 tiny FSMs?  Maybe I am wrong about the size of the FSMs.  Or maybe it  
would be practical to combine the clock gating to many of the 100,000 FSMs  
so they are shut off in large blocks?  I don't know, but the OP seems preoc
cupied with the idea of this being a language feature rather than a design  
feature added by the user.  I'm sure he wants to produce an idea using a li
brary or something that he can patent.  That seems to be his MO.  Oh well..
.  

  Rick C.

  - Get 6 months of free supercharging
  - Tesla referral code - https://ts.la/richard11209

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Sunday, January 6, 2019 at 11:23:10 AM UTC-8, snipped-for-privacy@gmail.com wr
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 chips the clock tree design can consume half the dynamic power in the chip
.  So gating the clock can bring significant power savings.  However, the c
lock gating being described here is over far too small a portion of the chi
p to be effective on many levels if I understand what is going on.  The OP  
is talking about 100,000 identical state machines, one for each cache item.
  I believe what he is talking about as FSMs are really just a handful of F
Fs but I'm not sure.  If so, the clock gating logic is nearly as large and  
so would consume nearly as much power and area as the logic it is controlli
ng.  
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00,000 tiny FSMs?  Maybe I am wrong about the size of the FSMs.  Or maybe i
t would be practical to combine the clock gating to many of the 100,000 FSM
s so they are shut off in large blocks?  I don't know, but the OP seems pre
occupied with the idea of this being a language feature rather than a desig
n feature added by the user.  I'm sure he wants to produce an idea using a  
library or something that he can patent.  That seems to be his MO.  Oh well
...  
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Hi Rick,
You misunderstand and ~100,000 state machines are even coded as the same bu
t with different input signals and output signals, act differently and you  
cannot "combine the clock gating to many of the 100,000 FSMs". Each has mor
e than 10 states, so each state machine must have 4 registers to implement  
and each has its clock gating logic and clock gating device.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/6/19 4:30 PM, Weng Tianxiang wrote:
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If you are really talking gating for 4 FFs, than my guess is that using
Clock Enabled ffs would be much simpler and probably better than trying
to gate the clock and keeping things synchronized.

The big issue would be that to make the gated clocking work you may need
double the clock distribution tree, one for an 'early' clock that is to
be gated, and a second 'late' clock that ungated parts of the system
used that will line up with the gated clocks. This need for the second
clock distribution tree probably eats up more power than you are saving
by stopping the clock to those flip flops.

The primary alternative to two clocks would be running on opposite edges
(so skew isn't as much of a problem), but that then limits the speed the
system can run at.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
I want to use my method in all types of circuits. A clock gating device is basically a latch. A FF with a clock enable input is a FF having a latch. Thank you.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/6/19 8:59 PM, Weng Tianxiang wrote:
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Unless you are using the term different than I am used to I would
disagree somewhat.

A "latch" is, to my language, and asynchronous memory unit that copies
it input to its output for one level of the enable, and the output holds
its current value for the other level of the enable. It is one of the
more primitive memory unit.

A latch could be used for clock gating, but is highly inefficient for
doing so, as the properly designed clock gate knows what state the
output should be in the gated off state, so doesn't need to the logic to
maintain current state. The clock gating device is basically a GATE.

There may be a way to use a latch to build a gated ff, but again, there
are simpler methods with better timing.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Richard,

I don't think so:
"The clock gating device is basically a GATE"!

Kevin,
"No, the number of state machines does not matter since they will (or shoul
d) be controlling much larger stuff that would consume the bulk of the powe
r.  If you have 100,000 state machines controlling 10,000 things in a data  
path, you likely have incompetently designed state machines. "

One state machine controls the status for a 64 bytes L2 cache line, and 100
,000 state machines fully control 6M L2 cache status. It does not control d
ata path! Their states will be affect how each of L2 cache line behaves.

If you have time have a look at the following 2 patents, at least you can u
nderstand what each of those 1000,000 state machines is and and how it work
s.

Thank you.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Sunday, January 6, 2019 at 4:30:27 PM UTC-5, Weng Tianxiang wrote:
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h clock gating function?
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current market) a CPU must have at least (2**16 + 2**15) state machines, ~
= 100,000, and those ~100,000 state machines don't change states most of  
time.
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having more than 10 states must have a clock gating function to save power  
consumption:  
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ip.  So gating the clock can bring significant power savings.  However, the
 clock gating being described here is over far too small a portion of the c
hip to be effective on many levels if I understand what is going on.  The O
P is talking about 100,000 identical state machines, one for each cache ite
m.  I believe what he is talking about as FSMs are really just a handful of
 FFs but I'm not sure.  If so, the clock gating logic is nearly as large an
d so would consume nearly as much power and area as the logic it is control
ling.  
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 100,000 tiny FSMs?  Maybe I am wrong about the size of the FSMs.  Or maybe
 it would be practical to combine the clock gating to many of the 100,000 F
SMs so they are shut off in large blocks?  I don't know, but the OP seems p
reoccupied with the idea of this being a language feature rather than a des
ign feature added by the user.  I'm sure he wants to produce an idea using  
a library or something that he can patent.  That seems to be his MO.  Oh we
ll...  
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but with different input signals and output signals, act differently and yo
u cannot "combine the clock gating to many of the 100,000 FSMs". Each has m
ore than 10 states, so each state machine must have 4 registers to implemen
t and each has its clock gating logic and clock gating device.

So you know what the clock gating circuity would look like?  Try comparing  
that circuit to the FSM circuit.  You will see they are comparable in size  
and the gating circuit adds to the timing delay as well.  

Please keep in mind that the 4 FFs in a single FSM can be lumped together w
ith the 4 FFs from another FSM in your analysis to consider them to be a si
ngle FSM for the purposes of clock gating.  When any one FSM is active you  
can make the entire circuit active.  This still retains the clock power sav
ings for all the remaining 99,998 FSMs not in that circuit.  

I'm not sure this will provide much in the way of logic savings.  But I am  
confident no one is going to want to implement clock gating circuits for ea
ch 100,000 FSMs independently.  But then it seems they are scrounging aroun
d for ways to improve power consumption of CPUs these days and there are lo
ts of transistors available.  I'm also a guy who thought cell phones would  
not be widely accepted. lol


  Rick C.

  + Get 6 months of free supercharging
  + Tesla referral code - https://ts.la/richard11209

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
If 2 state machines as you suggested may be active on the same clock, how do you handle it using your scheme?

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
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Weng - I find your obsession with "state machines" a bit puzzling.  I
seem to recall an poster a few years ago asking about the "largest"
state machine in current designs - was this you?  It seems likely, in
the event that you consider a CPU cache as a large number (~100,000)
of state machines running in parallel.

I've not designed a CPU cache.  But I can pretty much guarantee that
whomever designed that CPU cache you're thinking about did NOT model  
the design as such (a lot of state machines running in parallel).  To
be frank, I can see the entire design being done without implementing  
a "state machine" at all.

A state machine is simply a model to make it easier for humans to
understand and design a circuit.  It's not neccesary at all to apply
this model to any or all digital circuits.  

One of my co-workers (for whatever reason) abhors "State machine"  
design, and won't use them - at all.  That's fine, he models things  
differently.  And he's a very productive engineer - not hindered one bit
by his lack of use of "state machines".  

Conversely, one can model an entire ASIC (or FPGA) design as simply
one large state machine.  Or many smaller state machines running in
parallel.  (Assume a single clock for this analogy). It's just that a  
model to aid our (the designers) view of a design.  

Take a full schematic of any full ASIC.  Draw a random blob around ANY
set of 4-5 FFs.  Include some parts of the fanin and fanout logic
of those flip flops.  Bam - there's a state machine.  Repeat 20,000
times for all FF's in the design.  Is this useful - not really - but it
will meet any definition of "State Machine" that you can define.

Regard,

Mark



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