Can I store the output of my FPGA logic inside FPGA memory for debug data values?

Hi,

I am using altera FPGA.

How can I put the output of my logic into the FPGA internal memories(assuming I have unused memories available)?

Reply to
vlsi_learner
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Probably best to use a dual port RAM - something like a lpm_ram_dp will do nicely. Using the megawizard decide on the width and depth required. Set up a scanner (mux/counter combo) with each of your internal nodes that you want to store located on the input of the mux. Wizz round (scan) the mux inputs with your counter, at the same time using the counter output as the address to your RAM. Output of mux is data input to RAM. Also generate an appropriate clock/WR for the RAM. Bring the other side of the DPR address and DATA to the FPGA I/O and weld up the WR line low (you only want to READ). Now, assuming you internal scanned nodes have defined bit and address positions, and you have an appropriate scan sample rate going, you can access any node via the I/O address data lines.

Now why couldn't you think of that?

Icky

Reply to
Icky Thwacket

This sounds really complicated. He asked for putting the output into the memory, only. Looks like he don't want to read it back :-)

Looks like such things are common to people with gmail accounts.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

In which case he needs one of these:-

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Reply to
Symon

these:-

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Symon,

Thank you so much for that link. I saw this datasheet back in the 1970's with much amusement. I especially liked the filament voltage supply and cooling requirements. This one's going up on my wall :-)

Regards, Gabor

Reply to
Gabor

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Please can supply simulation model if haves?

Reply to
MikeWhy

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Writing a physical correct simulation model for the faucet, which you can see in the block diagram, would be really difficult in VHDL, but I guess the code below is a fairly good approximation. You can specify the size of the memory by specifying the address_width parameter when instantiating the entity and with data_width you can specify the number of bits per element. Default is a memory of 4294967296 bytes.

When synthesizing, it has an exceptional low LE count, works with very fast clocks and last but not least: This works for both, as simulation model and with real FPGAs!

entity WriteOnlyMemory is generic ( address_width: integer := 32; data_width: integer := 8 ); type address_type is unsigned(address_width - 1 downto 0); type data_type is unsigned(data_width - 1 downto 0); port( address: in address_type; data: in data_type; clock: in std_logic; write_enable: in std_logic ); end entity WriteOnlyMemory;

architecture rtl of WriteOnlyMemory is begin signal the_storage: data_type; write_process: process(clock) variable temp: data_type begin if rising_edge(clock) then if write_enable = '1' then temp := 0; for i in 0 to address loop temp := temp xor data; end loop; end if; the_storage

Reply to
Frank Buss

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