Hi, I am learning FPGA by a DSP book (1st edition) written by Uew Meyer_Baese. There is an example about 16 bit adder with detailed timing parameters, such as: tco=0.2 ns, tcgen=1.5ns tcico=0.3ns, tsamerow=2.9ns, tLUT=1.9ns and tsu=2.7ns. The fmax of that 16 bit adder is 74.6 MHz I think it is EPF10K20RC240-4 from the context.
In my practice project, I can only see the IC(interconect) and CELL delay timing parameters from the timing closure floorplan. Because the fmax I get is lower (only 59.52 MHz from timing analyzer) than that in the book, I want to know the difference. The purpose is I want to be ensure whether I get the fast 16 bit adder. BTW, I post my code below. Because the timing parameters give tco etc., I use register at the input and output ports.
Could you help me? Thanks in advance.
LIBRARY lpm; USE lpm.lpm_components.ALL;
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL;
ENTITY add16 IS GENERIC (WIDTH : INTEGER := 16; -- Total bit width ONE : INTEGER := 1); -- 1 bit for carry reg. PORT (x,y : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); -- Inputs sum : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); clk : IN STD_LOGIC); END add16;
ARCHITECTURE flex OF add16 IS SIGNAL sum0, q2, q1 -- LSBs of inputs : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); BEGIN reg_1: lpm_ff -- Save LSBs of x+y and carry GENERIC MAP ( LPM_WIDTH => WIDTH ) PORT MAP ( data => x, q => q1,clock => clk ); reg_2: lpm_ff GENERIC MAP ( LPM_WIDTH => WIDTH ) PORT MAP ( data => y, q => q2, clock => clk );
-------------- First stage of the adder ------------------ add_1: lpm_add_sub -- Add LSBs of x and y GENERIC MAP ( LPM_WIDTH => WIDTH, LPM_REPRESENTATION => "UNSIGNED", LPM_DIRECTION => "ADD") PORT MAP ( dataa => q1, datab => q2, result => sum0); reg_3: lpm_ff GENERIC MAP ( LPM_WIDTH => WIDTH ) PORT MAP ( data => sum0, q => sum, clock => clk );
END flex;