My Virtex5 design has a clock from an input pin going to a PLL that generates several clocks at different frequencies. My design treats these as asynchronous clocks, so I don't want the ISE timing analyzer to work on timing for the registers that cross clock domains. I can write the timespecs as unrelated in my ucf, but ngdbuild always traces the input clock into the PLL, and generates additional constraints for the PLL output clocks that are all related. So timing analyzer reports timing violations on my clock domain crossings.
In the past, I have put a TIG on every register that crosses clock domains, and that works. But it seems like if I could only make ngdbuild accept my (unrelated) PERIOD specs, instead of generating its own (related) specs, then it would be simpler to maintain. Anyone know how to control this in ngdbuild?