Hi:
The simplest incarnation of a 2-to-1 multiplexer can be described by the equation:
y = ~s & a | s & b
where 'y' is the output, 's' is the select input, with 'a' and 'b' the data inputs.
Of course, this multiplexer is broken because a practical implementation glitches in a if 'a' and 'b' are true, and the select line toggles. Such as this example from the book (1):
----------------------------------------- module mux21g ( input wire a, input wire b, input wire s, output wire y );
wire _s; wire c, d;
assign #10 _s = ~s; assign #10 c = _s & a; assign #10 d = s & b; assign #10 y = c | d;
------------------------------------
The fix for the glitching is of course to implement an extra term (Verilog not shown, but I think we can all handle it):
y = ~s & a | s & b | a & b
So the big questions are:
- What happens (ie., synthesizes) when you implement these equations in an FPGA?
1a. What synthesizes if you do:
assign y = ~s & a | s & b; // ???
1b. What synthesizes if you code the corrected mux equation:assign y = ~s & a | s & b | a & b; // ???
1c. Is there any difference in the synthesis if you code it one bitwise operation at a time, like the module above, vs. all in one equation?1d. If you "infer" a mux using the code shown in the vendor's device library, then do you get a good mux, or a glitchy mux?
In the case of a CPLD, I would expect that I could implement the fixed mux if I selected suitable synthesis properties, such as "mux extraction" (which I think recognizes my intent to create a mux, perhaps whether I code it glitch free or not, and implements a correct mux--can any tool experts clarify?) and/or "wysiwyg" which will probably even implement the bad mux if I so choose.
But the FPGA with its LUTs is a different ball of wax.
I will be extremely interested to hear what the experts make of these questions.
I think that it is possible, though I don't yet know how, to see the "RTL" output by the synth? Are the answers to my questions to be found there?
Then there are pre-synthesis and post-synthesis (or is it pre and post fitting?) simulation models, etc., and whew! There are quite a few things I haven't delved into yet.
Have a nice weekend!
(1) "Learning by Example using Verilog ..." Richard Haskell, et.al. pg. 78.
Disclaimer -- none of the above is intended to imply that one should ever route a clock through logic such as a mux!