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Call VHDL module from Verilog

Hi,

I have a basic question. Is is possible in the xilinx ISE enviroment to make a verilog wrapper of some VHDL code. I don't want to recode it in verilog.

Thanks Rob

Reply to
egadget1
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Never mine I figured it out.

Rob

Reply to
egadget1

The rule is, you have to tell us what you did ;)

Reply to
Mike Treseler

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