Greetings, all,
I have read through many postings about bypass/decoupling capacitors for Xilinx FPGAs at comp.arch.fpga. It seems to me common "solution" (there are many, I'm sure) to use at most 10 or 20 caps for the entire FPGA, of one value of one size (i.e.: 0.1 uF or 0.33 uF capacitor, 0603 package, perhaps). I guess I just want a quick a dirty suggestion of what best to do (in terms of bypass caps) for this board. It's goal is to be a small board (current size is 2 by 5 inches or less) and only has the most basic components: two SRAM modules, an EEPROM module, power regulation via a TPS75003, an oscillator, and a few miscellaneous components (LEDs, etc.) with the rest of the free pins on the Spartan 3 (PQ208 package) becoming User I/O pins.
The goal is to be as small as possible, and the board will be used by students (like myself) on projects as an alternative to a microprocessor solution (though the Spartan-3 will likely be configured with Microblaze). Also, right now I'm limiting myself to just four layers, with the one inner layer as a GROUND plane and the other as a VCCO plane. I doubt we'll use the board for really high- speed projects (in the gigahertz range...), but regardless I still have doubts as to what caps to use.
I know there are many, many postings of similar topics as this one but I just need confirmation that I can "get away" with using as few bypass caps as possible. There are discussions relating to more advanced electrical concepts that I do not fully understand, and some real-world experience and recommendation concerning my board setup and chip selection would be greatly appreciated.
Thanks. Lue Her University of St. Thomas (St. Paul, MN)