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Bus macro problem in dynamic partial reconfiguration

Hi!

I encounter a strange problem that I haven't been able to solve for several days of hard work. I'm using a Spartan2 in order to achieve dynamic partial reconfiguration, but my design doesn't work even if it passes through all the steps successfully.

I think that the problem comes from my bus macro (released by Xilinx with XAP 290) that it isn't correctly included in my design after the very first mapping. My design includes two modules and therefore only two bus macro (one for each direction), but one of them is divided in two part (two wires are mapped in respect of the macro, but the two others are mapped in another position).

Grégory Mermoud snipped-for-privacy@epfl.ch Master Student Computer Science Departement I&C Faculty Swiss Federal Institute of Technology - Lausanne

Reply to
Grégory Mermoud
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Hi Grégory, Sorry, I've no idea how to help you, but I just wondered if anyone outside of academe has used partial reconfiguration? Successfully? I briefly looked back through CAF, and most of the P_R posters I found had edu/ac addresses. Cheers, Syms.

Reply to
Symon

Hi!

I solved my problem about bus macro. In fact, my macro was not well placed since I choosed

INST "busRegToInc" LOC = "TBUF_R25C17.1" ; INST "busIncToReg" LOC = "TBUF_R26C17.1" ;

Using xdl, I noticed that Xilinx uses TBUF number 0 and not 1 in their macro. Then, I wrote

INST "busRegToInc" LOC = "TBUF_R25C17.0" ; INST "busIncToReg" LOC = "TBUF_R26C17.0" ;

and my macro got well placed and shaped. The problem is now that my design doesn't work, despite of the fact that it seems completely correct in FPGA editor. I don't understand why, but I will keep you informed.

Thank you,

Grégory

P.S. : my assistant has successufully achieved such design, but it seems that he has never encountered such problem.

Sym> Hi Grégory,

Reply to
Grégory Mermoud

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