Hello All,
I have 3 burning, if fundamental questions about FPGA architecture.
1) When the term routing is used, does it include the switch block multiplexers and the interconnections (Long wires, short wires etc.)?2) When packing it done well, can I say that LUTs are packed close to each other so the amount of routing resources used is less?
3) For Altera FPGAs (eg. Stratix versions), how are the LUTs implemented? For Xilinx, its generally distributed RAM. For Altera which only uses coarse-grain memory, this can't be the case so what is the alternative?tEd