Burning Questions- FPGA architecture, packing, LUTs....

Hello All,

I have 3 burning, if fundamental questions about FPGA architecture.

1) When the term routing is used, does it include the switch block multiplexers and the interconnections (Long wires, short wires etc.)?

2) When packing it done well, can I say that LUTs are packed close to each other so the amount of routing resources used is less?

3) For Altera FPGAs (eg. Stratix versions), how are the LUTs implemented? For Xilinx, its generally distributed RAM. For Altera which only uses coarse-grain memory, this can't be the case so what is the alternative?

tEd

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Ted
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I normally am referring to both the interconnect lines as well as the switches and multiplexors when I use the term routing.

You would thinks so. But I am sure there are mitigating factors. For example, if you have large data busses that need to run on long routes anyway, it is not so important to minimize the length of these nets while other logic such as FSM (finite state machines) will be well served by short routes. So it is a design dependant issue.

I believe the LUTs are still RAM based in Altera FPGAs. You just can't use the LUT as a small ram block. I expect Xilinx has a patent on that. But patents expire eventually. So it may not be too long before Altera also has distributed ram... likely about the time when no one cares anymore ;)

--
Rick "rickman" Collins

rick.collins@XYarius.com
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rickman

Different architectures are different, but I would include everything except LUT data bits, carry chain configuration, and IOB configuration. Inputs to LUT's, FF's, and IOB's usually come from mux's, which are, to me, routing.

Maybe. If you use the carry chain that fixes the relative position of many CLBs. That can restrict the routing such that close packing increases the routing problems.

Also, as the device gets full and routing resources get low, the router can make some very long routes, including through LUTs.

If the device is not very full, there isn't much constraint on the routing and some routers will spread the logic out.

It is, I believe, a course array of RAM, DSP, and LAB blocks, where the LAB blocks internally contain LUT's and routing resources, and then routing between the different kinds of blocks.

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-- glen

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glen herrmannsfeldt

Hi Glen, Rick,

I can see what you guys are saying. Thanks for the clarification about semantics. I think that the bit about packing is very interesting. I agree that the dependence of routing resources on packing is dependant on the amount of routing and logic resources left over but I guess that the more efficiently the logic is packed, the slower we will hit the threshold that would place severe constraints on routing and mapping. Correct me if I am wrong.

Also, the part on the use of carry chains could produce routing problems make sense. However, if the carry chain is not used, more routing resources would need to be used to link the carries from 1 cell to another. For arithmetic rich operations, this could be a problem.

It seems to me that relationship between routing resources and packing efficiency is pretty strong across most aplications. Again, feel free to refute me. Thanks.

tEd

Reply to
Ted

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