Buggy behaviour in Modelsim, when reading from pipe?

Hi All,

I had to integrate a VHDL testbench of complex system with the Python software (which is used to control the real hardware). Additionally it had to be done in portable way. Therefore I've decided to use pipes to establish communication between the Python software and VHDL simulator.

Everything works perfectly with GHDL (I can share my solution if anyone is interested in it) but when I tried to use it with Modelsim in our lab, I faced serious problem. It seems, that there is something wrong with reading from the pipe in the Modelsim. The Modelsim reads only a few messages form the pipe, and then it claims, that the end of file has been reached, even though the sending end of the pipe is still active. Maybe Modelsim opens the pipe in non-blocking mode? Or maybe there is something wrong with the endfile function?

Unfortunately Modelsim is not opensource, so probably it will be difficult to fix the problem, but maybe someone has found any workaround? Maybe the problem may be fixed by wrapping any libc routines with dynamic library preloaded with LD_PRELOAD? Maybe the problem maybe fixed somehow in the textio package?

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TIA & Regards,
Wojtek Zabolotny
Reply to
Wojciech Zabolotny
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Send them a bug report and test case.

Cheers, Jon

Reply to
Jon Beniston

I've finally managed to solve the problem by opening the pipe in the foreign subprogram, and by setting the mode to blocking with the fcntl function.

[...] rdpipe=open("./rdpipe",O_WRONLY); flags = fcntl( wrpipe, F_GETFL ); flags &= ~O_NONBLOCK; fcntl( wrpipe, F_SETFL, flags ); [...]

However it required to use the FLI interface, which impaired portability of the design.

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BR, Wojtek
Reply to
Wojciech Zabolotny

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