Hi !
In the spartan datasheet I can read that:
"Horizontal routing resources are provided for on-chip
3-state busses. Four partitionable bus lines are provided per CLB row"What does partitionable mean in this case ? Does this mean the horizontal lines can be divided ? If so, where (how many) the division points are there ?
Is FPGA Editor removed from ISE6.1i ? I've recently used 6.1i at my university, and couldn't find it :(