Folks,
I observe a curious problem on my FPGA Build on Virtex 5 FPGA and would lik e to understand if any of you had seen this before.
As part of SoC Emulation, I have coded my FPGA RTL with a bunch of Clock Bu ffers (in order to emulate Clock Gating on internal logic) which was consum ing about 10 Buffers. This design build was working on the platform as expe cted and I wanted to free-up the BUFGs for other usage and hence eliminated the initial bunch of them by commenting them out replacing them with direc t assign statements with no clock enable. Though the Build result reflected reduction in the BUFG count, I saw that the FPGA Logic is continuously hel d on POR and is not getting released for operations. I use the clock direct ly from the IO and do not use any DCM/PLL. I have used one BUFG for the Asy nchronous Reset from the IO which is ANDed with another IO signal.
Did someone else come across this kind of observation?
Appreciate everyone's response.
regards, Venkat.