I have created two BRAM using coregen (BLK_MEM_GEN_V2_4) , out of them #1 is not supporting byte enable #2 supports byte enable Both of them are of same size 512x32
Now, during simulation the read data coming out of the BRAM #2 is not the one which has been written. In BRAM #1, the read_data is same as written data. The only difference in between them is usage of byte wide write enable.
I can't find why this is happening? can anyone please help me in finding out the real problem.
ISE Version : 9.2i
Below are the files which i am using...
=================================================== BRAM #1, =================================================== `timescale 1ns/1ps
module xil_syn_ram( clka, dina, addra, ena, wea, //clkb, addrb, enb, doutb);
input clka; input [31 : 0] dina; input [8 : 0] addra; input ena; input [0 : 0] wea; //input clkb; input [8 : 0] addrb; input enb; output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_4 #( .C_ADDRA_WIDTH(9), .C_ADDRB_WIDTH(9), .C_ALGORITHM(1), .C_BYTE_SIZE(9), .C_COMMON_CLK(0), .C_DEFAULT_DATA("0"), .C_DISABLE_WARN_BHV_COLL(0), .C_DISABLE_WARN_BHV_RANGE(0), .C_FAMILY("virtex5"), .C_HAS_ENA(1), .C_HAS_ENB(1), .C_HAS_MEM_OUTPUT_REGS(0), .C_HAS_MUX_OUTPUT_REGS(0), .C_HAS_REGCEA(0), .C_HAS_REGCEB(0), .C_HAS_SSRA(0), .C_HAS_SSRB(0), .C_INIT_FILE_NAME("no_coe_file_loaded"), .C_LOAD_INIT_FILE(0), .C_MEM_TYPE(1), .C_PRIM_TYPE(1), .C_READ_DEPTH_A(512), .C_READ_DEPTH_B(512), .C_READ_WIDTH_A(32), .C_READ_WIDTH_B(32), .C_SIM_COLLISION_CHECK("ALL"), .C_SINITA_VAL("0"), .C_SINITB_VAL("0"), .C_USE_BYTE_WEA(0), .C_USE_BYTE_WEB(0), .C_USE_DEFAULT_DATA(0), .C_USE_ECC(0), .C_USE_RAMB16BWER_RST_BHV(0), .C_WEA_WIDTH(1), .C_WEB_WIDTH(1), .C_WRITE_DEPTH_A(512), .C_WRITE_DEPTH_B(512), .C_WRITE_MODE_A("WRITE_FIRST"), .C_WRITE_MODE_B("NO_CHANGE"), .C_WRITE_WIDTH_A(32), .C_WRITE_WIDTH_B(32), .C_XDEVICEFAMILY("virtex5")) inst ( .CLKA(clka), .DINA(dina), .ADDRA(addra), .ENA(ena), .WEA(wea), .CLKB(clka), .ADDRB(addrb), .ENB(enb), .DOUTB(doutb), .REGCEA(), .SSRA(), .DOUTA(), .DINB(), .REGCEB(), .WEB(), .SSRB(), .DBITERR(), .SBITERR());
// synthesis translate_on
endmodule
=================================================== BRAM #2, ===================================================
`timescale 1ns/1ps
module xil_syn_ram_be( clka, dina, addra, ena, wea, // clkb, addrb, enb, doutb);
input clka; input [31 : 0] dina; input [8 : 0] addra; input ena; input [3 : 0] wea; //input clkb; input [8 : 0] addrb; input enb; output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_4 #( .C_ADDRA_WIDTH(9), .C_ADDRB_WIDTH(9), .C_ALGORITHM(1), .C_BYTE_SIZE(8), .C_COMMON_CLK(0), .C_DEFAULT_DATA("0"), .C_DISABLE_WARN_BHV_COLL(0), .C_DISABLE_WARN_BHV_RANGE(0), .C_FAMILY("virtex5"), .C_HAS_ENA(1), .C_HAS_ENB(1), .C_HAS_MEM_OUTPUT_REGS(0), .C_HAS_MUX_OUTPUT_REGS(0), .C_HAS_REGCEA(0), .C_HAS_REGCEB(0), .C_HAS_SSRA(0), .C_HAS_SSRB(0), .C_INIT_FILE_NAME("no_coe_file_loaded"), .C_LOAD_INIT_FILE(0), .C_MEM_TYPE(1), .C_PRIM_TYPE(1), .C_READ_DEPTH_A(512), .C_READ_DEPTH_B(512), .C_READ_WIDTH_A(32), .C_READ_WIDTH_B(32), .C_SIM_COLLISION_CHECK("ALL"), .C_SINITA_VAL("0"), .C_SINITB_VAL("0"), .C_USE_BYTE_WEA(1), .C_USE_BYTE_WEB(1), .C_USE_DEFAULT_DATA(1), .C_USE_ECC(0), .C_USE_RAMB16BWER_RST_BHV(0), .C_WEA_WIDTH(4), .C_WEB_WIDTH(4), .C_WRITE_DEPTH_A(512), .C_WRITE_DEPTH_B(512), .C_WRITE_MODE_A("WRITE_FIRST"), .C_WRITE_MODE_B("READ_FIRST"), .C_WRITE_WIDTH_A(32), .C_WRITE_WIDTH_B(32), .C_XDEVICEFAMILY("virtex5")) inst ( .CLKA(clka), .DINA(dina), .ADDRA(addra), .ENA(ena), .WEA(wea), .CLKB(clka), .ADDRB(addrb), .ENB(enb), .DOUTB(doutb), .REGCEA(), .SSRA(), .DOUTA(), .DINB(), .REGCEB(), .WEB(), .SSRB(), .DBITERR(), .SBITERR());
// synthesis translate_on
endmodule
=================================================== Testbench, both above modules are instantiated in it ===================================================
module design_top_tb_v;
// Inputs reg clka; reg clkb; reg [31:0] dina; reg [8:0] addra; reg wea; reg [3:0] wea_be; reg [8:0] addrb; reg ena; reg enb;
// Outputs wire [31:0] doutb; wire [31:0] doutb_be;
parameter PERIOD = 20; parameter DUTY_CYCLE = 0.5;
// Instantiate the Unit Under Test (UUT) xil_syn_ram uut ( .clka(clka), //.clkb(clkb), .dina(dina), .addra(addra), .wea(wea), .addrb(addrb), .ena(ena), .enb(enb), .doutb(doutb) );
xil_syn_ram_be uut_be ( .clka(clka), //.clkb(clkb), .dina(dina), .addra(addra), .wea(wea_be), .addrb(addrb), .ena(ena), .enb(enb), .doutb(doutb_be) );
// Clock Stimulus always begin clka = 1'b0; #(PERIOD-(PERIOD*DUTY_CYCLE)) clka = 1'b1; #(PERIOD*DUTY_CYCLE); end
// Clock Stimulus always begin clkb = 1'b0; #(PERIOD-(PERIOD*DUTY_CYCLE)) clkb = 1'b1; #(PERIOD*DUTY_CYCLE); end
initial begin // Initialize Inputs clka = 0; clkb = 0; dina = 0; addra = 0; wea = 0; wea_be = 0; addrb = 0; enb = 0; ena = 0;
// Wait 100 ns for global reset to finish #120; ena = 1; enb = 1;
wea_be = 4'b0001; wea = 1'b1;
// 120 ns addra = 4'b0000; addrb = 4'b1111;
// 140 ns #20 addra = 4'b0001; addrb = 4'b1110;
// 160 ns #20 addra = 4'b0010; addrb = 4'b1101;
// 180 ns #20 addra = 4'b0011; addrb = 4'b1100;
// 200 ns #20 addra = 4'b0100; addrb = 4'b1011;
// 220 ns #20 addra = 4'b0101; addrb = 4'b1010;
// 240 ns #20 addra = 4'b0110; addrb = 4'b1001;
// 260 ns #20 addra = 4'b0111; addrb = 4'b1000;
// 280 ns #20 addra = 4'b1000; addrb = 4'b0111;
//Overwrite of memory from INIT Values #280
// 570 ns #10 addra = 4'h0; dina = 16'h1010;
addrb = 4'h0;
// 590 ns #20 addra = 4'h2; dina = 16'h23F2;
addrb = 4'h2;
// 610 ns #20 addra = 4'h4; dina = 16'h2514;
addrb = 4'h4;
// 630 ns #20 addra = 4'h6; dina = 16'h1616;
addrb = 4'h6;
// 650 ns #20 addra = 4'h8; dina = 16'h1818;
addrb = 4'h8;
// 670 ns #20 addra = 4'hA; dina = 16'h1A1A;
addrb = 4'hA;
// 690 ns #20 addra = 4'hC; dina = 16'h1C1C;
addrb = 4'hC;
// 710 ns #20 addra = 4'hE; dina = 16'h1E1E;
addrb = 4'hE;
// 730 ns #20 $finish; end
endmodule