Boundary scan

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I can't find any Maxim 28544 (nor MAX28544) part, but if this part does not have a JTAG interface then any board level testing will be incomplete. You should be able to test if there is a short, but you won't be able to test if the FPGA is connected to the Maxim part.

There are mutiple vendors that provide JTAG PCB software solutions as a quick Google search will show:

-- Xilinx Inc.

There's a simple method to check for open circuits on FPGA IO pins. If you can get to the net on the board surface somewhere (at the Maxim part?) you can use a multimeter in diode-check mode. Connect the positive multimeter lead to ground and the negative lead to the net under test. You should be able to read the forward drop of the ground clamp diode in the FPGA this way. Normally you would need to disconnect other loads from the net, but if the ground clamps on the Maxim part have a higher Vf, then you should be able to tell if some FPGA pins are not connected even without removing the other part. I've found that the Vf of the clamps of any given part are quite consistent, so even 100 mV above the other readings is enough to tell you that a pin is disconnected.

-- Gabor

(snip)

The usual way to test I/O devices like serial ports is to put a loop-back plug into the connector, send a signal out, and see if the right signal comes back. That requries a little outside help, but also tests more parts.

-- glen